The upper grid seal layer is deposited as a thin, conformal coating to encapsulate the metal grid and prevent light obstruction in the optical stack .
In depth
In advanced backside-illuminated (BSI) CMOS image sensors, the optical stack requires strict physical and optical isolation between adjacent pixel
s to minimize crosstalk and ensure high spatial resolution . Preceding process steps involving tungsten (W) and TiN etching define the metallic light shield and grid structures that provide this critical optical isolation (Engineering Practice). Following the ashing and stripping steps that remove photoresist and post-etch residues, the Upper Grid Seal Layer Deposition step is performed to completely encapsulate the exposed upper surfaces of this metal grid . Unlike the Oxide Grid Seal Layer Deposition, which primarily acts as the bulk dielectric gap-fill between the grid lines, or the LS/Aperture Grid Deposition steps that form the bulk metal barrier and core, this Upper seal layer specifically caps the top topography of the completed grid . This encapsulation acts as a vital chemical and mechanical barrier between the highly reactive grid metals and the subsequent wet chemical processes, such as Pre Litho Cleaning and organic Color Filter Array (CFA) coating . The deposition mechanism typically relies on forming a highly conformal dielectric film over the steep topography of the etched grid structure . Plasma-enhanced atomic layer deposition (PEALD) or plasma-enhanced chemical vapor deposition (PECVD) methods are frequently utilized due to their low-temperature capabilities and excellent conformality on high-aspect-ratio surfaces . During this process, precursor gases undergo plasma-assisted dissociation and surface-limited reactions to form a dense, low-permeability dielectric network . This layer functions analogously to a hermetic packaging material, presenting a polymer-like or dielectric barrier with extremely low permeability that inhibits the diffusion of moisture and particulate contaminants . By establishing this barrier, the seal layer prevents aqueous solutions used in subsequent lithography and color filter steps from oxidizing the underlying tungsten core . Furthermore, the deposition process can help passivate residual dangling bonds and surface states left behind by the aggressive physical ion bombardment of the preceding TiN and W etch steps, reducing localized interface trap density ($D_{it}$) that could otherwise distort pixel electrostatics . The selection of material for the upper grid seal layer involves a stringent trade-off between optical transparency, conformality, and moisture barrier performance (Engineering Practice). Silicon nitride or silicon oxynitride is frequently selected because it provides superior chemical resistance and moisture-blocking properties compared to standard thermal or deposited silicon dioxide (Engineering Practice). Alternatively, incorporating thin high-k dielectrics can also provide dense, pinhole-free sealing at highly scaled thicknesses, though their fixed charge properties must be carefully managed to avoid unintended field-effect polarization of nearby structures . Process parameters such as plasma power, precursor flow rates, and deposition temperature directly dictate the resulting film density and intrinsic stress . A delicate balance is necessary: excessive plasma power can induce high-energy ion damage and generate unwanted border traps in the underlying sensor interfaces , whereas insufficient plasma density results in a porous, structurally weak film that fails to protect the grid from chemical ingress during CFA processing (Engineering Practice). At the 40nm BSI technology node, pixel dimensions are highly scaled, demanding maximized fill factors and ultra-thin optical stacks to ensure optimal photon collection . Because the structural dimensions of the metallic light shield are rigorously constrained by design rules, the upper seal layer must be extremely thin yet flawlessly conformal to prevent obstruction of the incident light path to the photodiode . Consequently, achieving atomic-level control over the deposition thickness is paramount, as any unintended thickness variation directly alters the optical interference path length, translating to optical non-uniformity and degraded quantum efficiency across the sensor array .
Risks & Challenges
[High] Grid Metal Oxidation and Corrosion: If the upper seal layer exhibits poor step coverage or pinholes, subsequent aqueous pre-lithography cleaning and CFA developing processes can penetrate the barrier . This allows moisture to react directly with the underlying W/TiN grid, leading to volumetric expansion from metal oxidation and subsequent physical degradation of the optical stack .
[Medium] Plasma-Induced Interface Damage: High-energy plasma bombardment during the PEALD or PECVD deposition process can generate UV radiation and charged particles that penetrate the substrate . This exposure risks creating new interface traps ($D_{it}$) and border traps, which can act as generation-recombination centers and undesirably increase the dark current of the imager .
[Medium] Film Delamination from Thermomechanical Stress: Mismatches in the coefficient of thermal expansion (CTE) and high intrinsic film stress between the metallic grid and the deposited dielectric can cause mechanical failure . Analogous to stress failures in complex packaged layers, concentrated thermomechanical stress can lead to the peeling or cracking of the seal layer prior to the color filter coating .
[Low] Optical Transmittance Degradation: Variations in the precursor gas stoichiometry or insufficient plasma reaction energy can alter the composition and refractive index of the deposited seal layer . This unintended shift in the material's optical properties can induce parasitic reflections or undesirable light absorption, ultimately reducing the quantum efficiency of the underlying pinned photodiode .