40nm BSI CMOS Image SensorPreview

l and electrical crosstalk [P2]. To mitigate this, a deep opaque isolation structure—often referred to as a vertical grid or light shield (LS)—is constructed between pixels (Engineering Practice). This step, "Upper Vertical Grid Deposition," involves depositing the bulk opaque material that constitutes the upper portion of this photon-blocking wall (Engineering Practice). It immediately follows the "Upper Vertical Grid Barrier Deposition," which prevents interaction between the grid metal and the surrounding dielectric, and prepares the wafer for the subsequent "Upper Vertical Grid - Photo" and "W Etch" steps where the final grid geometry is patterned [A1]. This step is distinct from the "Lower Vertical Grid Deposition" because high-aspect-ratio isolation in advanced nodes often requires a multi-tier approach to overcome gap-fill limitations and prevent voiding in a single continuous trench (Engineering Practice). The deposition of the upper vertical grid relies on Chemical Vapor Deposition (CVD) to ensure a conformal coating over the substrate (Engineering Practice). The bulk metal, typically Tungsten (W), is deposited through the reduction of tungsten hexafluoride by hydrogen or silane (Engineering Practice). The core physical mechanism is the formation of a continuous, highly absorptive physical barrier that reflects or absorbs laterally traveling photons, effectively reducing optical crosstalk and improving the spatial resolution of the sensor [P3]. This optical isolation is complementary to the electrical isolation provided by internal potential barriers [P1] or physical structures like buried oxides [A2]. The thickness and structural integrity of this deposited film directly determine the subsequent etch loading and the final optical opacity of the grid (Engineering Practice). Tungsten is overwhelmingly selected for the vertical grid due to its high optical extinction coefficient across the visible and near-infrared spectrum (Engineering Practice). Unlike Copper (Cu), which is primarily used for back-end interconnects to optimize electrical readout performance [P3], W can be deposited conformally into complex topologies without severe diffusion risks into the adjacent silicon (Engineering Practice). The CVD method is chosen over Physical Vapor Deposition (PVD) because PVD suffers from line-of-sight limitations, leading to pinch-off and void formation in deep structures (Engineering Practice). Process parameters such as temperature, precursor partial pressures, and carrier gas flow rates must be strictly balanced (Engineering Practice). Higher deposition temperatures increase the reaction rate but can induce excessive tensile stress in the thick metal film, potentially leading to wafer warpage or delamination at the barrier interface [T2]. At the 40nm node, the pixel pitch is drastically reduced, necessitating precise structural management to maintain acceptable optical focal depth and angular response [P3]. A multi-tier grid (lower and upper) is required because etching and filling a single ultra-deep trench at these minimal dimensions exceeds the fundamental aspect ratio capabilities of standard plasma etch and CVD systems (Engineering Practice).