A chemically amplified photoresist (CAR) is typically utilized, wherein photon absorption generates acid catalysts that subsequently alter the polymer's solubility during the post-exposure bake, allowing for sub-micron feature resolution .
Following the deposition of the backside passivation (BP
MD SiO) and pre-litho cleaning, the Backside Substrate Contact - Photo step defines the localized openings required to electrically ground the silicon substrate of the BSI image sensor . This step is distinct from front-side contact patterning (such as Metal 0/1 Source/Drain Contacts) because it operates on the chip's backside, defining pathways that will eventually be filled with metal to create deep vias traversing the thick dielectric stack . Establishing these backside connections is critical for providing a low-resistance path to the substrate, which minimizes pixel cross-talk and stabilizes the substrate potential during image capture . The lithographic pattern must be precisely aligned to the buried front-end structures, ensuring that the subsequent deep etch through the BPMD SiO and high-K anti-reflective layers (TaO/AlO) lands exactly on the designated P+ or N+ substrate landing pads without damaging adjacent pixel arrays . The patterning process relies on optical projection lithography, where the fundamental resolution is governed by the Rayleigh criterion, scaling directly with the exposure wavelength and inversely with the numerical aperture . A chemically amplified photoresist (CAR) is typically utilized, wherein photon absorption generates acid catalysts that subsequently alter the polymer's solubility during the post-exposure bake, allowing for sub-micron feature resolution . Because this step patterns features over a relatively thick backside dielectric stack compared to standard FEOL layers, maximizing the depth of focus (DOF) and maintaining robust exposure latitude are critical . Furthermore, optical reflections from the underlying high-K layers (TaO) can cause constructive and destructive interference; this is mitigated by the application of a Bottom Anti-Reflective Coating (BARC) prior to resist coating, which optically absorbs excess energy to minimize standing waves and line-edge roughness . The selection of a thick nanoscale photoresist system for this step is driven by the physical requirement to serve as a robust mask for the subsequent multi-layer plasma etch (BPMD SiO, TaO, and AlO) . Because anisotropic plasma etching involves high-energy ion bombardment that physically sputters and aggressively consumes the mask, the resist must possess sufficient initial thickness and structural integrity to prevent premature erosion . However, increasing resist thickness directly degrades the lithographic resolution limit by exceeding the system's depth of focus, necessitating a careful optimization of the dose and focus parameters . Any organic residues or micro-loading effects resulting from incomplete development can cause the subsequent nanoscale etch to stop prematurely, as localized polymer accumulation inside high-aspect-ratio features inhibits the transport of reactive species down to the etch front . In the 40nm BSI CMOS image sensor architecture, the backside substrate contact must navigate strict geometrical constraints without compromising the optical fill factor of the pixel array . The shift of routing and grounding connections to the backside essentially extends the device into a three-dimensional structure, alleviating front-side routing congestion as described in principles of backside interconnect scaling . Consequently, the lithography process must carefully balance overlay accuracy—compensating for any mechanical wafer distortion induced during the wafer thinning and carrier bonding processes—with the high aspect ratio required for the eventual deep via formation .
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