40nm BSI CMOS Image SensorPreview

HKD/AR1 Etch

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RIE etch, Si Back etch

LS Backside Contact Ion Implantation
310Pre Litho Cleaning311Backside Substrate Contact - Photo312BPMD Etch313HKD/AR2 Etch314HKD/AR1 Etch315RIE etch, Si Back etch316LS Backside Contact Ion Implantation317Ashing & Strip/Clean

Process Cross-Section

ISP WaferCIS Wafer · BacksideSBST_CONT · Si Back Etch (to p-well)PRBPMDTaOAlOP+ implanted regionSiCESLSiO2CuTaAlSiN

Step highlight

Silicon RIE typically employs halogen-based chemistries, where chlorine or fluorine provides the primary reactive species, while bromine by-products are often utilized to passivate the trench sidewalls .

In depth

In 40nm BSI CMOS Image Sensor manufacturing, the wafer is inverted and bonded to a carrier so

that backside interconnects and contacts can be formed . After sequentially etching through the backside dielectric layers, including the BPMD and the high-k/anti-reflective (HKD/AR) stacks, this specific step etches into the bulk silicon substrate to form the localized backside contact trench . Unlike global substrate thinning or the SWS Nitride Anisotropic Back Etch which targets specific dielectric spacer structures, this step selectively removes patterned monocrystalline silicon . This structurally defines the contact region and prepares the exposed silicon surface for the subsequent LS Backside Contact Ion Implantation (IIP) step . The subsequent implantation is strictly required to highly dope the surface, enabling tunneling and lowering the effective barrier to form a reliable ohmic contact, consistent with fundamental metal-semiconductor contact physics . The physical mechanism of this step relies on Reactive Ion Etching (RIE), which utilizes a synergistic combination of active chemical radicals and directionally accelerated ions generated in a low-pressure discharge plasma . Because the silicon crystal structure features strong covalent bonding governed by its periodic potential , pure chemical etching by neutral radicals is prone to severe lateral etching and poor dimensional control . Therefore, accelerated ion bombardment from the plasma is required to physically break surface atomic bonds, lower the chemical reaction activation energy, and stimulate the formation of volatile etch products . Silicon RIE typically employs halogen-based chemistries, where chlorine or fluorine provides the primary reactive species, while bromine by-products are often utilized to passivate the trench sidewalls . This passivation blocks lateral chemical attack, allowing the directional ions to dominate the vertical etch rate and achieve highly anisotropic, vertical profiles . Dry RIE is strictly preferred over wet chemical etching methods for this structural level . Conventional wet etching is fundamentally limited by crystal orientation dependencies, while advanced metal-assisted chemical wet etching heavily depends on catalyst nanoparticle morphology, which degrades process stability and controllability at sub-micron dimensions . Furthermore, precise dimensional scaling and alignment are critical to avoid perturbing adjacent active structures, making the advanced profile control offered by decoupled plasma RIE systems indispensable . However, the use of highly energetic ions forces a physical trade-off between etch rate, profile verticality, and plasma-induced surface damage . For a 40nm BSI image sensor, controlling this plasma-induced damage is the primary optimization constraint . Structural defects in the silicon lattice, caused by excessive ion bombardment, create mid-gap energy states that act as generation-recombination centers . In the context of a photodiode array, these trap states directly manifest as unacceptably high dark current and isolated white pixel defects, severely degrading sensor performance (Engineering Practice). Consequently, the RF bias voltage and plasma chemistry must be tightly regulated to ensure the resulting trench is free of severe crystalline damage , while the subsequent ashing and wet clean steps are specifically positioned to remove any remnant fluorocarbon or brominated polymeric residues left on the silicon surface .

Risks & Challenges

  • [High] Plasma-Induced Damage (PID) and Dark Current: Energetic ion bombardment inherently disrupts the periodic atomic arrangement of the silicon crystal, creating lattice defects and dangling bonds . In BSI image sensors, these structural defects act as carrier generation centers, directly increasing device dark current and producing defective pixels (Engineering Practice).
  • [Medium] Loss of Profile Anisotropy (Sidewall Bowing): If the balance between halogen chemical etching and sidewall polymer passivation is lost, the directional ions cannot effectively suppress lateral etching . Insufficient bromine or polymer by-product passivation leads to lateral undercut, which can cause the backside contact structure to physically widen and short to adjacent isolated regions .
  • [Medium] RIE Lag and Micro-masking Effects: Variations in the local pattern density or the presence of incomplete residues from the preceding HKD/AR etch steps can act as physical micro-masks during the silicon etch . This leads to the RIE-lag effect, where trench depths vary significantly across the array, resulting in non-uniform backside contact resistance .
  • [Low] Charge-up Damage (Antenna Effect): The continuous accumulation of charged plasma ions on localized insulating surfaces within the trench structure can induce extremely high local electric fields . If unmitigated, these localized fields can couple through the substrate and cause electrostatic stress or breakdown in the ultra-thin front-side gate dielectrics .

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Related steps

  • Pre Litho Cleaning
  • Backside Substrate Contact - Photo
  • BPMD Etch
  • HKD/AR2 Etch
  • HKD/AR1 Etch
  • LS Backside Contact Ion Implantation