40nm BSI CMOS Image SensorPreview

relies fundamentally on establishing a near-ideal interface between the silicon channel and the gate dielectric [T1]. Following the high-energy ion implantations used for well formation and threshold voltage adjustment, the uppermost layers of the silicon substrate invariably suffer from lattice damage and embedded contaminants [A1]. To remediate this, a sacrificial oxidation step is previously performed to deliberately consume the compromised silicon and convert it into a sacrificial oxide (SACOX) layer, a technique proven to smoothen silicon walls damaged by preceding processes [A1]. The SACOX Removal step is strictly required at this juncture to completely strip away this contaminant-laden oxide layer, exposing a pristine, atomically smooth silicon surface [A1]. By effectively resetting the substrate condition, this step prepares the active area for the subsequent growth of the highly sensitive thin gate oxide [T2]. If this step is omitted, the accumulated defects would permanently degrade the surface mobility of channel carriers and compromise the structural integrity of the final gate stack [T2]. The physical removal of the sacrificial oxide is predominantly executed using a wet-chemical etching process based on highly diluted hydrofluoric acid (DHF) [P1]. The core chemical mechanism involves the fluoride ions aggressively attacking the silicon-oxygen bonds within the amorphous SiO2 network, converting the solid oxide into water-soluble fluorosilicate complexes that are easily rinsed away [P3]. This wet-chemical approach is favored because it is a kinetically controlled, isotropic dissolution process that avoids the plasma-induced lattice damage inherent to dry etching methods [P3]. Crucially, the HF chemistry exhibits extremely high selectivity to the underlying crystalline silicon, as it cannot readily break the strong Si-Si bonds [P2]. Upon completely clearing the oxide, the HF solution inherently leaves the exposed silicon surface terminated with hydrogen atoms [P2]. This temporary hydrogen passivation acts as a chemical shield, suppressing the spontaneous regrowth of low-quality native oxide and preventing interface contamination while the wafer awaits transfer to the oxidation furnace [P3]. The selection of a highly diluted HF concentration over more aggressive etchants or dry methods is driven by the strict necessity for atomic-level surface control [P3]. Because modern advanced technologies rely on ultra-thin gate dielectrics where the equivalent oxide thickness (EOT) is scaled to near physical limits, even minor surface roughening directly accelerates tunneling leakage and compromises reliability [T3]. A diluted wet chemistry ensures that the reaction rate remains heavily governed by surface chemical kinetics rather than mass transport, granting the sub-nanometer etch control required to prevent excessive substrate pitting [P3]. Furthermore, the etch time and chemical concentration must be precisely balanced against the inevitable collateral etching of the adjacent insulating dielectric structures [A2]. Overextending the process time leads to an excessive recess of the shallow trench isolation (STI) oxide, which physically alters the isolation geometry and induces parasitic corner conduction paths in the active device [A2]. At the 40nm technology node, specifically for Back-Illuminated (BSI) CMOS Image Sensors, minimizing surface defects during SACOX removal is highly critical to reducing overall pixel noise [A2]. As device dimensions scale down, the enhanced interface perpendicular electric fields cause channel carriers to be increasingly subjected to surface scattering, making inversion layer surface mobility significantly lower than bulk mobility [T2]. Any residual micro-roughness or incomplete oxide removal will locally amplify this scattering, drastically reducing the drive current (Ion) capabilities of the pixel read-out transistors [T2]. Furthermore, stringent control over the subthreshold leakage current (Ioff) is mathematically mandated by thermodynamic scaling limits, as off-state leakage depends exponentially on the gate voltage's uniform control over the surface potential [T3]. Therefore, achieving an absolutely pristine and geometrically uniform silicon surface during SACOX removal is a non-negotiable physical prerequisite for maintaining the necessary signal-to-noise ratio and static power constraints in advanced integrated circuits [T3].