40nm BSI CMOS Image SensorPreview

te oxide thicknesses; core devices rely on scaled thin oxides to maximize drive current and switching speed, while I/O or pixel transistors need thick oxides to withstand higher operating voltages and prevent tunneling leakage [T1]. The Nitride Hard Mask Etch step is explicitly designed to transfer the photolithographic Dual Gate Oxide (DGOX) boundary pattern into the silicon nitride layer [A2]. By selectively removing the nitride, this step exposes the specific active areas where the thick gate oxide will be thermally grown, while the remaining nitride serves as a resilient oxidation barrier for the thin-oxide regions [A2]. Unlike a generic sidewall spacer etch that targets a conformal thickness [P1], or an isotropic wet removal step, this DGOX hard mask etch must achieve highly precise anisotropic pattern transfer while stopping flawlessly on a thin underlying pad oxide to protect the sensitive silicon substrate [P4]. The physical and chemical mechanism of this step relies on reactive ion etching (RIE), which combines the chemical reactivity of plasma radicals with the directional momentum of accelerated ions [P4]. Fluorocarbon-based gas mixtures (such as CHF3 combined with O2 or CO2) are predominantly utilized to generate fluorine radicals that volatilize the Si-N bonds [P4]. To balance anisotropy and selectivity, the process typically employs a two-step sequence [P4]. The first step operates under higher ion bombardment to rapidly clear the bulk of the silicon nitride and maintain vertical sidewalls, ensuring strict critical dimension (CD) fidelity [P4]. As the etch front approaches the pad oxide interface, the process switches to a highly selective second step with a higher ratio of polymerizing gases [P4]. This creates a differential reaction where silicon dioxide surfaces are passivated by fluorocarbon polymers, whereas silicon nitride continues to etch, preventing the plasma from punching through the pad oxide [P4]. Preventing underlying silicon exposure is critical, because reactive ion bombardment creates localized lattice damage that serves as nucleation sites for stacking faults and edge dislocations during the subsequent thermal oxidation [P4]. Silicon nitride is specifically chosen as the hard mask material because of its dense atomic structure, which effectively blocks oxygen diffusion during the subsequent high-temperature thick gate oxide growth [A2]. Dry etching is selected over wet etching to eliminate isotropic undercutting, ensuring that the critical linewidth of the DGOX boundary is accurately maintained [P4]. Process parameters such as RF bias power, chamber pressure, and gas ratios define the crucial trade-off between etch rate, chemical selectivity, and structural profile [P4]. Increasing the proportion of polymerizing precursors enhances the SiN-to-SiO2 etch selectivity, but excessive polymerization risks micro-masking and incomplete nitride removal [P4]. Conversely, increasing the RF bias power improves the verticality of the etch profile but degrades selectivity, thereby elevating the risk of pad oxide consumption and silicon substrate damage [P4]. For a nanoscale Backside Illuminated (BSI) CMOS Image Sensor, minimizing interface defect density is paramount to sensor performance [P2]. Any crystalline damage or surface roughness transferred into the silicon substrate during this hard mask etch will translate into interface trap states [T2]. These trap states critically degrade subthreshold swing [T1] and act as primary generation centers for pixel dark current and white pixel defects (Engineering Practice). Consequently, managing cross-wafer etch rate non-uniformity and accurately timing the transition to the selective overetch are essential to prevent localized silicon pitting across the massive pixel array [P4].