40nm BSI CMOS Image SensorPreview

different operating voltages [P1]. Following the photolithographic patterning and subsequent dry etching of the nitride hard mask, a thick layer of polymerized photoresist and fluorocarbon etch residues remains on the wafer surface [A3]. This specific Ashing & Strip/Clean step is positioned precisely to eradicate these organics and polymers before the high-temperature thick gate oxide growth [P1]. If the photoresist and etch byproducts are not thoroughly removed, residual carbon and metallic impurities will be incorporated into the silicon substrate during the subsequent thermal oxidation, severely degrading the gate oxide integrity [P1]. This step is distinct from other strip processes in the flow because its immediate downstream process is a critical thermal oxidation, which has near-zero tolerance for surface micro-roughness or contamination [P1]. The ashing and strip/clean sequence employs a two-stage physical-chemical mechanism to ensure pristine surface conditions (Engineering Practice). First, an oxygen-based plasma ashing process is typically used to rapidly oxidize and volatilize the bulk organic photoresist, converting carbon-based polymers into gaseous byproducts like CO and CO2 [A2]. However, plasma ashing alone is insufficient to remove the heavily cross-linked fluorocarbon polymers generated during the preceding nitride hard mask dry etch (Engineering Practice). Therefore, the subsequent wet clean relies on highly oxidative chemistries, such as a Sulfuric Peroxide Mixture (SPM), which leverages the strong oxidizing power of H2SO4 and H2O2 to chemically decompose the remaining stubborn organic contaminants [P1]. This exothermic reaction efficiently breaks carbon-carbon bonds while maintaining excellent selectivity, virtually leaving the underlying exposed materials unetched [P1]. The selection of SPM over traditional alkaline cleans like the Ammonia Peroxide Mixture (APM) is driven by the need to preserve the surface planarity of the active areas [P1]. APM contains NH4OH, which provides hydroxide (OH−) ions that chemically etch SiO2 and silicon surfaces, inducing surface micro-roughness [P1]. In advanced nodes, this induced roughness acts as a source of local electric field enhancement, which directly reduces the breakdown voltage and compromises the long-term reliability of the gate dielectric [P1]. Consequently, an SPM-centric wet clean is preferred here, as the process temperature, chemical composition, and immersion time can be co-optimized to maximize organic removal efficiency without degrading the surface [P1]. Careful control of the ashing plasma power and gas mixture is also necessary to prevent plasma-induced physical damage or deep implantation of resist impurities into the substrate [A3]. At the 40nm technology node, the equivalent oxide thickness (EOT) requirements dictate that even sub-nanometer levels of surface degradation or contamination will exponentially increase gate leakage currents [P2]. As the thick gate oxide region undergoes a complex grow-etch-regrow cycle inherent to dual-gate integrations, the exposed surfaces are highly sensitive to the chemicals used during the strip and clean phases [P1]. Any localized defect or trapped charge resulting from incomplete cleaning will shift the threshold voltage and exacerbate short-channel effects, making stringent control of this strip/clean step vital for overall device yield and functionality [T1].