Instead, targeted chemistries are employed to decompose organic contaminants via strong oxidative reactions while preserving the original surface planarity .
As CMOS technology moves toward multiple voltages, the dual-gate-oxide process becomes inevitable . In the 40nm BSI CMOS Image Sensor f
low, differentiating high-voltage and low-voltage transistor regions requires highly precise patterning . This specific Pre Litho Cleaning occurs immediately after Nitride Hard Mask Deposition and right before the Thick Gate Oxide photolithography step . Unlike other pre-litho cleans in the flow that prepare bare silicon or gate oxides, this step uniquely targets a deposited silicon nitride surface to remove adventitious particles and organic trace residues prior to resist coating . Ensuring a pristine nitride surface prevents localized masking failures during the subsequent Nitride Hard Mask Etch, which would otherwise translate into physical damage or undesirable etching of the underlying active structural layers . The physical objective of this cleaning step is to eliminate surface particulates and organic residues without altering the thickness or profile of the silicon nitride hard mask . Traditional cleaning mixtures containing NH4OH can cause chemical etching of dielectrics by OH− ions, which induces surface micro-roughness . Instead, targeted chemistries are employed to decompose organic contaminants via strong oxidative reactions while preserving the original surface planarity . If highly cross-linked organic residues or polymer precursors from the deposition chamber are present on the surface, processing solutions containing specific solvent systems and trace metal ions can be introduced to promote the swelling and stripping of these contaminants . Furthermore, the cleaning process modifies the surface energy of the silicon nitride, optimizing the contact angle for the subsequent photoresist spin-coating step, a process fundamentally governed by intermolecular forces and surface adsorption behavior . Chemical selection must strictly balance contaminant removal efficiency against dielectric integrity . Solutions relying on strong oxidative reactions, such as sulfuric peroxide mixtures (SPM), are frequently selected in advanced processes because they efficiently decompose organics while exhibiting virtually zero etch rate on dielectric films . Process parameters such as cleaning temperature, time, and chemical composition directly determine both the organic removal efficiency and the risk of surface damage . The ionic strength of the cleaning solution can be fine-tuned to achieve a balance between selective contaminant removal and the physical protection of the underlying dielectric film . By executing this clean correctly and preventing unwanted surface reconstructions, the integrity of the mask and the subsequent device stack is protected from defect-induced degradation . At the 40nm node, the physical scaling limit requires extremely precise control over equivalent oxide thickness (EOT) and gate leakage . Because this specific photo step defines the boundaries of the dual-gate oxide regions, any lithography defect caused by a poor pre-clean can lead to misaligned hard mask etching and the subsequent formation of local electric field enhancement points that severely reduce breakdown voltage . Furthermore, minimizing surface roughness and contamination at this stage prevents the propagation of nanoscopic defects into the underlying layers during subsequent stripping and re-oxidation cycles . This rigorous defect control is fundamental to maintaining stable electrical reliability and predictable band structures in advanced CMOS architectures .
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