As CMOS technology moves toward multiple voltages, the dual-gate-oxide process becomes inevitable P1.In the 40nm BSI CMOS Image Sensor flow, differentiating high-voltage and low-voltage transistor regions requires highly precise patterning P4.This specific Pre Litho Cleaning occurs immediately after Nitride Hard Mask Deposition and right before the Thick Gate Oxide photolithography step P1.Unlike other pre-litho cleans in the flow that prepare bare silicon or gate oxides, this step uniquely targ