40nm BSI CMOS Image SensorPreview

rocess flow, the interlayer dielectric (ILD) stack typically consists of an underlying SiCN etch stop/barrier layer and an overlying oxide or low-k ILD layer [A1]. The preceding step (ILD 4-2 Oxide Etch) etches down through the bulk oxide and stops precisely on this SiCN layer, utilizing the differential etch selectivity between the two dielectric materials [A1]. The "ILD 4-1 SiCN Etch" step is then required to selectively remove the exposed SiCN at the bottom of the Via 4 (V4) structure, exposing the underlying Metal 4 copper surface to enable the subsequent electrical connection to Metal 5 [P3]. Unlike lower-level etches (ILD 1-1, 2-1) which interact with denser local interconnect geometries, or upper-level etches (ILD 6-1) which deal with ultra-thick global routing layers, the V4 level balances intermediate pitch requirements with stringent resistance-capacitance (RC) delay constraints [T2]. By acting as a hermetic diffusion barrier, the SiCN layer prevents copper outward diffusion into the low-k dielectric and protects the copper surface from oxidation during the preceding oxide etch [P3]. Physically, the SiCN etch utilizes a fluorinated reactive ion etching (RIE) plasma, which operates through a combination of chemical reactions and physical ion bombardment [P1]. Fluorine atoms and CFx radicals generated in the plasma chemically react with the Si-C-N network to form highly volatile byproducts, such as SiF4, COx, and NOx, which are pumped out of the chamber [P1]. Simultaneously, directional ion bombardment breaks surface bonds and promotes the desorption of these reaction products, driving anisotropic profile evolution [P1]. A critical dynamic during this process is the deposition of a fluorinated polymer layer on the via sidewalls, formed by carbon-rich radicals, which protects the surrounding ILD oxide from lateral etching [P1]. Furthermore, fluorine-radical-based dry etching can cause localized fluorination of the adjacent exposed dielectric sidewalls, forming fluorosilicate glass (FSG) structures that can slightly modulate the effective dielectric constant and interfacial properties [A2]. The selection of specific fluorocarbon chemistries is dictated by the critical need to achieve high etch selectivity between the dense SiCN etch stop and the surrounding oxide or low-k ILD [P1]. Because low-k oxide materials often exhibit higher etch rates in standard fluorocarbon plasmas due to their lower density, tuning the plasma composition to increase polymerizing species is essential to prevent severe critical dimension (CD) loss [P1]. Process parameters such as bias power directly control the incident ion energy; increasing bias power enhances the physical removal of the protective polymer at the via bottom, accelerating the SiCN breakthrough but potentially causing physical sputtering of the underlying copper [P4]. Conversely, adjusting the chamber pressure and gas ratios modulates the chemical radical concentration, balancing the competing mechanisms of volatile byproduct formation and surface passivation [P1]. At the 40nm node for BSI CMOS Image Sensors, minimizing interconnect RC delay is a primary constraint, making the integration of low-k dielectrics and ultra-thin SiCN barrier layers strictly necessary [P3]. As device dimensions shrink, the increased capacitive coupling between adjacent via layers directly impacts signal propagation speed and dynamic power consumption [T2]. Consequently, the SiCN layer must be kept as thin as possible while maintaining its mechanical integrity and barrier properties [P3]. Because the V4 intermediate routing layer faces tight alignment margins, the SiCN etch must be highly selective to avoid eroding the surrounding low-k dielectrics, which are extremely sensitive to plasma-induced damage and structural pore collapse [P2].