40nm BSI CMOS Image SensorPreview

[P1]. During the preceding main contact etch, the thick pre-metal dielectric (PMD) is removed, and the etch process is designed to selectively terminate on the Contact Etch Stop Layer (CESL) to prevent damage to the underlying active regions and gate structures [A1]. In advanced technologies, the CESL is often deposited via PECVD as a highly stressed amorphous hydrogenated silicon nitride film to induce strain in the transistor channel, thereby altering the silicon lattice constant and enhancing carrier mobility [P1]. Because 40nm CMOS logic often employs a dual-CESL approach with distinct tensile and compressive films for nMOS and pMOS, overlapping regions necessitate sequential breakthrough steps, distinguishing this CESL 1 Etch from the preceding CESL 2 Etch [P1]. This step must cleanly punch through the bottommost CESL film to expose the underlying pad oxide without eroding the contact sidewalls or compromising the strain-inducing properties of the remaining CESL over the transistor [P1]. The physical mechanism of this step relies on highly directional reactive ion etching governed by ion-neutral cooperative reactions [P2]. To etch the silicon nitride CESL, a specialized plasma chemistry is utilized, generating reactive neutral species and energetic ions to break the strong Si-N bonds [P3]. As the contact aspect ratio increases, the transport of neutral etchants to the bottom of the trench is restricted by geometric shadowing, causing the etch rate to become strongly dependent on the aspect ratio rather than independently on the feature width [P2]. Consequently, the plasma parameters must provide sufficient ion kinetic energy to penetrate the high-aspect-ratio contact hole and drive the surface reactions [P3]. Simultaneously, the plasma chemistry must maintain a high selectivity to the underlying pad oxide to prevent premature consumption of the protective layer [A1]. This selectivity is typically achieved by the formation of a polymerizing passivation layer on the oxide surface, which inhibits further etching once the nitride is cleared, functionally similar to the deposition of an etch-inhibiting layer described in halogen-based plasma systems [P2]. The selection of an anisotropic dry etch over wet etching is driven by the stringent dimensional control required at the 40nm node, where lateral etching must be minimized to preserve the contact critical dimension [P2]. The RF source power is carefully calibrated to control the electron-impact ionization and dissociation rates, thereby determining the gas-phase concentration of reactive radicals [P3]. Meanwhile, the RF bias power is optimized to adjust the ion flux and bombardment energy, which directly influences both the forward etch rate and the surface neutralization probabilities at the bottom of the contact [P3]. If the bias power is too low, the process suffers from severe aspect-ratio-dependent etching (ARDE) or "RIE lag," leading to incomplete CESL removal in the narrowest contacts [P2]. Conversely, excessive ion energy can cause physical sputtering that punches through the underlying pad oxide, potentially damaging the silicide or the silicon substrate where carrier mobility is highly sensitive to lattice integrity and surface scattering [T1]. Furthermore, process stability must be continuously monitored to mitigate uncontrolled process drifts caused by the deposition and re-etching of silicon-containing byproducts on the reactor chamber walls [P3].