This lithography step defines the exact spatial coordinates where vertical contact vias will be etched through the Pre-Metal Dielectric (PMD) stack to connect the initial metallization layers to the transistor gate and source/drain (S/D) terminals A1.Following prior PMD deposition and chemical mechanical planarization (CMP), the wafer surface is rendered exceptionally flat to provide an optimal focal plane for high-resolution optical lithography P2.Unlike implant lithography steps that merely ma