40nm BSI CMOS Image SensorPreview

Ashing & Strip/Clean

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Ti/TiN Deposition

W Deposition
112Metal 0 Gate and S/D Contact Opening - Photo113PMD 3 Etch114PMD 2 Etch115PMD 1 Etch116CESL 2 - Etch117CESL 1 - Etch118Pad Oxide Etch119Poly/Si Back Etch120Ashing & Strip/Clean121Ti/TiN Deposition122W Deposition123W CMP124TiN/Ti CMP

Process Cross-Section

CONTACT · A10 · Ti/TiN Liner DepositionFD node (31P+)VT adjust (11B+, periphery channel)SiO2 liner (SACVD)SiO2 (SACVD bulk fill)n+ S/D (31P+)n+ N-well contact (31P+)p+ surface passivation (10B+)Liner SiO2 (RTP thermal)P-well (pixel array, 11B+)P-well (periphery, 11B+)PD N-well (31P+)N-well (periphery, 31P+)SiP-well (implanted region)Ti/TiN linerPMD 3 (SiO2 · CMP overburden)PMD 2 (SiO2 · body segment)PMD 1 (SiO2 · bottom segment)CESL 2 (SiNO)SiNCESL 1 (SiN)PolySWS pad ox (SiO2, PECVD)gate ox (SiO2, thermal)IO/HV gate ox (SiO2; relative thickness shown schematically; IO device not shown in this cross-section)n- LDD (31P+, self-aligned)P-pinning (11B+)P+ VSS contact (11B+)

Step highlight

CVD operates via a surface-reaction-limited mechanism of gas-phase precursors, achieving near-isotropic deposition on sidewalls and bottom corners to form a continuous and dense diffusion barrier .

In depth

Following the ashing and cleaning of high-aspect-ratio contact holes, the structure requires a cond

uctive interface to connect the silicon active areas to the subsequent tungsten plug . The Ti/TiN stack serves a critical dual purpose: the titanium (Ti) layer acts as an oxygen-gettering and adhesion layer, while the titanium nitride (TiN) layer acts as a diffusion barrier . Without this TiN barrier, the highly corrosive WF6 precursor used in the subsequent tungsten deposition step aggressively attacks the underlying Si or silicide interfaces, leading to volatile TiF4 byproduct formation and severe contact voiding . Furthermore, matching the metal work function of the contact metals to the underlying doped silicon is essential for reducing the Schottky barrier height and overall contact resistance, as defined by metal-semiconductor interface physics . Specifically, Ti and TiN provide favorable work-function alignments for n-type contacts, ensuring efficient carrier injection across the interface . The deposition of the TiN barrier layer in deep contacts heavily relies on chemical vapor deposition (CVD) rather than physical vapor deposition (PVD) due to severe geometric shadowing effects inherent to line-of-sight transport . CVD operates via a surface-reaction-limited mechanism of gas-phase precursors, achieving near-isotropic deposition on sidewalls and bottom corners to form a continuous and dense diffusion barrier . In advanced plasma-enhanced variants, the reaction is driven by high-density reactive species that selectively cleave precursor bonds rather than relying strictly on thermal equilibrium decomposition . This non-thermal plasma environment leverages electron impact to drive chemical reactions, allowing high-quality, crystalline TiN formation at reduced substrate temperatures . Selecting a highly conformal CVD TiN overlayer resolves the critical trade-off between step coverage and early electromigration failure caused by interfacial discontinuities . However, while TiN is chemically stable, its intrinsically high resistivity and nanocrystalline morphology introduce a significant series resistance penalty in nanometer-scale interconnects . Consequently, deposition parameters such as precursor partial pressure must be carefully optimized; excessively high deposition rates lead to incomplete reactions and impurity retention, causing a sharp increase in film resistivity . Additionally, the film's microstructural phase must be engineered, as polycrystalline TiN features grain boundaries that significantly lower diffusion barriers and act as rapid penetration pathways for subsequent metallization . At the 40nm node, the physical volume constraints of middle-of-the-line (MOL) contacts mean that conventional barrier layers occupy excessive effective conductive volume, further exacerbating line resistance limits . Therefore, the Ti/TiN thickness is strictly minimized to maximize the volume available for the lower-resistivity bulk tungsten fill . For Backside Illuminated (BSI) CMOS image sensors specifically, strictly controlling the thermal budget during this plasma-enhanced deposition is also essential to prevent dopant diffusion and structural degradation that could elevate dark current noise .

Risks & Challenges

  • [High] Contact Open via Precursor Attack: Insufficient conformality of the TiN barrier at the bottom corners of high-aspect-ratio contacts exposes the underlying interface to WF6 during subsequent processing . This triggers a severe chemical reaction that forms volatile TiF4, consuming the underlying titanium and silicon to create structural voids and electrical opens .
  • [High] Elevated Contact Resistance: Excessively fast TiN deposition kinetics prevent complete precursor decomposition, trapping unreacted ligands and organic impurities within the film lattice . These impurities, combined with the intrinsically high resistivity of nanocrystalline TiN, severely restrict the electron mean free path and exponentially increase the effective MOL interconnect resistance .
  • [Medium] Fermi Level Pinning at Interface: Incomplete titanium oxygen-gettering or poor pre-deposition clean leaves a high density of interface traps (Dit) at the metal-semiconductor boundary . These surface states pin the Fermi level and negate the work-function matching benefits of the Ti layer , yielding a high Schottky barrier and non-ohmic conduction .
  • [Low] Trans-Barrier Metal Diffusion: Sub-optimal plasma conditions during deposition can yield a highly columnar polycrystalline TiN microstructure . The resulting grain boundaries traverse the ultrathin film thickness, establishing direct channels for solid-state diffusion kinetics that compromise the barrier's protective function during later thermal cycles .

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Related steps

  • Metal 0 Gate and S/D Contact Opening - Photo
  • PMD 3 Etch
  • PMD 2 Etch
  • PMD 1 Etch
  • CESL 2 - Etch
  • CESL 1 - Etch