40nm BSI CMOS Image SensorPreview

ing the "Mid Vertical Grid Trench - Photo" step, the lithographic pattern must be transferred through intermediate layers before etching the underlying grid material (Engineering Practice). The "Lower OCL Coating Etch" specifically targets the organic planarization layer (OPL) or anti-reflective coating that was deposited to planarize the pixel array topography and reduce lithographic reflections [A2]. Unlike the actual "Lower OCL Etch," which directly shapes the lens or grid dielectric itself, this coating etch serves strictly as a pattern transfer step, amplifying the photoresist pattern into the thicker coating layer to form a robust mask for subsequent deep etching [P3]. The etching of organic coating layers typically utilizes an oxygen-based or fluorocarbon-based reactive ion etching (RIE) plasma [P3]. In an oxygen RIE process, oxygen radicals chemically react with the carbon-rich polymer coating to form volatile byproducts [P3]. To achieve a highly anisotropic profile, the etch relies on the synergistic effect of directional ion bombardment and chemical volatilization [P2]. If a silicon-containing anti-reflective coating or hard mask is present in the stack, fluorocarbon gases like CF4 or CHF3 are introduced to efficiently break the Si-O or Si-N bonds [P1]. The plasma source power controls the ion flux density, while the bias power dictates the ion bombardment energy, which directly influences the verticality of the etched sidewalls [P1]. Anisotropic RIE is selected over isotropic wet etching because precise critical dimension (CD) control is mandatory for the high-density nanoscale optical structures [T1]. The gas mixture, chamber pressure, and residence time are carefully balanced to optimize the etch rate and selectivity against the overlying photoresist [P1]. Adding specific passivating gases or adjusting the C/F ratio helps form a thin protective polymer on the sidewalls during the etch, preventing lateral undercut [P2]. Furthermore, strict control of the etching chemistry ensures that the sidewall roughness is minimized, which is critical to avoid subsequent optical scattering losses [P2]. The use of an etch stop layer or precise end-point detection prevents over-etching into the underlying optical pad [A1]. At the 40nm technology node, pixel pitch is aggressively scaled, limiting the thickness of the photoresist that can be reliably patterned without collapse [P3]. This multi-layer mask stack strategy is necessary because the ultra-thin photoresist required for sub-wavelength lithography cannot withstand the extended plasma exposure needed to etch deep grid trenches [P3]. Thus, the coating etch acts as a crucial geometric amplifier, converting a fragile, shallow resist pattern into a high-aspect-ratio polymer mask capable of shielding the active regions during the subsequent heavy dielectric etches [P3].