40nm BSI CMOS Image SensorPreview

OL) process responsible for forming the intermediate or semi-global routing interconnects in the 40nm BSI CMOS Image Sensor architecture [P4]. Unlike the Metal 0 Tungsten (W) step used for local contacts due to its high conformal fill in ultra-small vias [P1], and the Metal 1 to Metal 3 layers which feature minimum-pitch tight routing to minimize local cell area [T2], Metal 4 is typically designed with comparatively relaxed pitches to handle higher currents and route signals over longer distances across the sensor array (Engineering Practice). This step directly follows the deposition of a Ta-based diffusion barrier and a physical vapor deposited (PVD) Cu seed layer, which jointly prevent copper from diffusing into the surrounding low-k dielectrics and provide the necessary cathode conductivity [A1]. Following this electrochemical fill, the wafer proceeds to Chemical Mechanical Planarization (CMP) to remove the copper overburden and isolate the individual metal lines [P2]. The physical and chemical operation of this step relies on wet electrochemical deposition (ECD), which utilizes a precisely controlled multicomponent additive system to achieve void-free, "bottom-up" filling of the dual-damascene structures [P2]. An applied electric field drives Cu2+ ions through the aqueous bath toward the wafer, where they gain electrons and undergo reduction to form solid copper atoms on the cathode surface [P4]. To prevent conformal growth that would pinch off the top of the trench and leave a void, the plating bath contains an inhibitor, typically polyethylene glycol (PEG), and an accelerator, such as bis(3-sulfopropyl) disulfide (SPS), along with chloride ions [P2]. On short time scales, transient diffusion and geometric constraints limit the transport of the bulky inhibitor molecules into the deep via, resulting in lower inhibitor coverage and a relative enrichment of the accelerator at the feature bottom [P2]. This localized accelerator enrichment significantly increases the bottom deposition rate compared to the top, initiating a self-sustaining bottom-up growth front [P2]. Electrochemical wet deposition is universally selected over PVD or chemical vapor deposition (CVD) for bulk copper fill because it offers superior step coverage and gap-filling capability without the formation of key-hole defects [P4]. Copper itself replaces aluminum in these advanced interconnects due to its substantially better electrical conductivity and electromigration resistance, both of which are critical for maximizing device functionality and long-term reliability [P4]. The microstructural quality of the deposited copper, particularly the dominance of the low-resistivity, highly reliable Cu(111) crystallographic orientation, is strongly influenced by the reaction kinetics and the purity of the bath chemistry [P4]. In-situ optical monitoring of the plating solution's color, specifically hue and saturation, can be employed to track the real-time decomposition of additives and the depletion of Cu2+ species [P4]. By dynamically adjusting the applied current density and additive replenishment based on these chemical states, the process ensures optimal crystal growth while suppressing the accumulation of performance-degrading impurities [P4]. At the 40nm node, specific scaling challenges emerge because the overall device performance becomes highly sensitive to interconnect RC delays and variation [T2]. For a semi-global layer like Metal 4, the dual-damascene trenches exhibit different aspect ratios and widths compared to the tightly pitched Metal 1, requiring a tailored balance of PEG and SPS diffusion fluxes to ensure uniform fill across varying feature sizes [P2]. Furthermore, systematic variations originating from upstream lithography, such as optical proximity effects, can alter local pattern densities across the die [T2]. These pattern density variations directly influence local electric field distributions and additive consumption rates during electroplating, dictating that the deposition recipe must incorporate multi-step current waveforms to maintain a globally uniform overburden thickness prior to CMP [P4].