VIA 5 - Photo - 40nm BSI CMOS Image Sensor 40nm

because the low-k dielectrics used to minimize RC delay possess poor mechanical strength, the photoresist must exhibit excellent adhesion and structural integrity to prevent pattern collapse .

VIA 5 - Photo defines the vertical interconnects bridging Metal 5 and Metal 6 in the dual-damascene back

-end-of-line (BEOL) stack . Coming immediately after the ILD 5-1 and ILD 5-2 depositions and a pre-litho clean, this step spatially defines the contact openings before pattern transfer into the underlying dielectric layers . The precise positioning of these vias is critical to establish low-resistance electrical connections for signal and power routing within the image sensor architecture (Engineering Practice). Subsequent dry etching steps rely entirely on the polymeric resist mask generated here to selectively remove the ILD 5-2 oxide and ILD 5-1 SiCN layers . The lithographic process leverages optical diffraction principles and photochemical reactions to transfer the reticle pattern to the wafer . A tri-layer stack comprising an organic planarization layer (OPL), an anti-reflective coating (ARC), and a photoresist is typically spin-coated onto the planarized ILD surface . Exposure to ultraviolet light triggers a localized chemical reaction within the photoresist . In chemically amplified positive resists, photoacid generators release acid that catalyzes the deprotection of the polymer matrix during the post-exposure bake, rendering the exposed regions soluble in the developer . The resolution limit of this pattern transfer is governed by the Rayleigh criterion, which dictates the minimum resolvable feature size based on the exposure wavelength and the numerical aperture of the lens system . Material selection for the photolithography stack is driven by the need to control reflectivity and maintain mechanical stability . The ARC layer is essential to suppress standing waves caused by thin-film interference at the resist-dielectric interface, which would otherwise degrade the via sidewall profile . Furthermore, because the low-k dielectrics used to minimize RC delay possess poor mechanical strength, the photoresist must exhibit excellent adhesion and structural integrity to prevent pattern collapse . Process parameters such as exposure dose and focus depth strongly interact; deviations in these parameters can lead to variations in critical dimensions (CD) or incomplete resist clearing, directly impacting the subsequent etch module's ability to form the via without systematic defects . At the 40nm node, the physical spacing between adjacent vias and metal lines shrinks significantly, amplifying the risk of Time-Dependent Dielectric Breakdown (TDDB) driven by high electric fields . Consequently, lithography overlay misalignment becomes a dominant yield detractor, as standard deviations in edge placement error directly reduce the physical dielectric spacing between a via and a neighboring metal line . To mitigate this, the via photo process must strictly adhere to design rules governing via density and alignment tolerances . Additionally, misalignment can lead to scenarios where the via etches into unintended bottom dielectrics or leaves planarization material residues, forming potential leakage paths at the weak cap-layer/low-k interface .

[High] Lithography Overlay Misalignment (Edge Placement Error): Misalignment during the lithography process causes the via pattern to shift relative to the underlying metal layer . This reduces the dielectric spacing between the via and adjacent metal lines, significantly degrading the breakdown voltage and leading to premature Time-Dependent Dielectric Breakdown (TDDB) . If the misalignment is severe, the via may etch into the bottom dielectric, exposing the cap-layer/low-k interface to moisture and copper diffusion .
[High] Photoresist Pattern Collapse or Missing Patterns: High-aspect-ratio via patterns patterned in the photoresist are susceptible to capillary forces during the drying phase of the development step . Poor surface planarity or inadequate gap-filling of underlying topography exacerbates resist thickness non-uniformity, mechanically destabilizing the resist and causing it to collapse . This defect propagates into the etch step, resulting in missing vias and electrical open circuits .
[Medium] Standing Wave Effects and Poor Sidewall Profiles: Highly reflective underlying metal and dielectric layers cause the incident UV light to interfere with reflected light, creating standing waves within the photoresist layer . Without a properly optimized anti-reflective coating (ARC), this periodic exposure variation creates a scalloped or highly sloped resist sidewall . This degraded profile transfers into the dielectric during etching, causing via chamfering and increasing parasitic capacitance .
[Low] Incomplete Resist Development (Scumming): Insufficient exposure dose or suboptimal post-exposure bake temperatures can leave the polymer deprotection reaction incomplete at the bottom of the via pattern . The unreacted resist residue prevents the developer from fully clearing the via hole (Engineering Practice). This blocks the subsequent plasma etch chemistry, resulting in a partially etched dielectric and an electrical open circuit .

because the low-k dielectrics used to minimize RC delay possess poor mechanical strength, the photoresist must exhibit excellent adhesion and structural integrity to prevent pattern collapse .

VIA 5 - Photo defines the vertical interconnects bridging Metal 5 and Metal 6 in the dual-damascene back

[High] Lithography Overlay Misalignment (Edge Placement Error): Misalignment during the lithography process causes the via pattern to shift relative to the underlying metal layer . This reduces the dielectric spacing between the via and adjacent metal lines, significantly degrading the breakdown voltage and leading to premature Time-Dependent Dielectric Breakdown (TDDB) . If the misalignment is severe, the via may etch into the bottom dielectric, exposing the cap-layer/low-k interface to moisture and copper diffusion .
[High] Photoresist Pattern Collapse or Missing Patterns: High-aspect-ratio via patterns patterned in the photoresist are susceptible to capillary forces during the drying phase of the development step . Poor surface planarity or inadequate gap-filling of underlying topography exacerbates resist thickness non-uniformity, mechanically destabilizing the resist and causing it to collapse . This defect propagates into the etch step, resulting in missing vias and electrical open circuits .
[Medium] Standing Wave Effects and Poor Sidewall Profiles: Highly reflective underlying metal and dielectric layers cause the incident UV light to interfere with reflected light, creating standing waves within the photoresist layer . Without a properly optimized anti-reflective coating (ARC), this periodic exposure variation creates a scalloped or highly sloped resist sidewall . This degraded profile transfers into the dielectric during etching, causing via chamfering and increasing parasitic capacitance .
[Low] Incomplete Resist Development (Scumming): Insufficient exposure dose or suboptimal post-exposure bake temperatures can leave the polymer deprotection reaction incomplete at the bottom of the via pattern . The unreacted resist residue prevents the developer from fully clearing the via hole (Engineering Practice). This blocks the subsequent plasma etch chemistry, resulting in a partially etched dielectric and an electrical open circuit .

40nm BSI CMOS Image SensorPreview

Process Cross-Section

Step highlight

In depth

Risks & Challenges

40nm BSI CMOS Image SensorPreview

Process Cross-Section

Step highlight

In depth

Risks & Challenges