40nm BSI CMOS Image SensorPreview

ubsequent Ti deposition [T1]. The preceding fluorocarbon-based dry etch leaves behind carbon-rich polymeric residues (CFx) and chemically damaged silicon surfaces [P3]. If not removed, these residues act as tunneling barriers, exponentially increasing specific contact resistivity [T1]. Therefore, this ashing and strip/clean step is specifically designed to eliminate plasma-induced polymers and sub-surface damage, ensuring a pristine silicon interface for titanium silicidation [P3]. This distinguishes it from mid-line bulk ashing steps, as it directly impacts active device contact resistance rather than merely performing bulk photoresist removal [P1]. The cleaning process relies on a sequence of oxidative and selective dissolution mechanisms [A1]. First, an oxygen-based plasma ashing is employed to oxidize the organic and carbon-based fluorocarbon polymers into volatile byproducts like CO and CO2 [P3]. However, ashing alone is insufficient because high-energy plasma etching chemically implants carbon and fluorine into the silicon lattice, forming strong Si-C and Si-F bonds in the top substrate layers [P3]. To remove this damaged layer, a subsequent wet chemical treatment is required, often utilizing dilute HF to strip the thin sacrificial oxide generated during the O2 ashing [P3]. This oxidize-and-remove cycle selectively consumes a precisely controlled nanometer-scale layer of the damaged silicon, exposing the underlying pristine lattice without causing excessive source/drain junction deepening [P3]. The sequence of O2 plasma followed by HF and an ammonia-hydrogen peroxide mixture (APM) is carefully chosen to balance residue removal with structural integrity [P3]. High-temperature ashing can cause crosslinking and hardening of polymeric residues, making them harder to strip, so temperature must be optimized to prevent defect formation [P1]. The APM step further removes residual fluorinated or carbon-bonded species through mild, controllable chemical etching of the silicon [P3]. Simultaneously, the chemistry must maintain high selectivity to the surrounding dielectric spacer materials to prevent spacer erosion and subsequent leakage currents [P3]. Furthermore, managing the chemical bath lifetime is critical, as dissolved materials can accumulate and redeposit, altering the etch kinetics and degrading the contact interface [A3]. At the 40nm node, the contact area is extremely small, meaning the specific contact resistance strictly dominates the total parasitic resistance [T1]. For highly doped contacts where field emission dominates, the presence of even sub-nanometer residual oxides or damaged silicon will drastically increase the effective barrier width [T1]. Thus, the atomic-level cleanliness achieved by this step is a non-negotiable prerequisite for the subsequent Ti/TiN/W deposition sequence [A1].