40nm BSI CMOS Image SensorPreview

ion module [A1]. Preceded by the sequential etching of upper pre-metal dielectric layers (PMD 4 through 2), this specific step targets the lowest SiO2-based layer of the dielectric stack [P1]. The primary objective is to complete the high-aspect-ratio contact holes while stopping reliably and uniformly on the underlying Contact Etch Stop Layer (CESL), which is typically composed of silicon nitride [P4]. Stopping exactly on the CESL is critical to protect the underlying active source/drain regions and gate structures from kinetic ion damage, utilizing selective reactive ion etching (RIE) principles that prevent unintentional consumption of the substrate [A1]. This precisely controlled depth allows subsequent steps to clear the CESL and pad oxide, ultimately ensuring a low-resistance ohmic contact pathway that minimizes specific contact resistance and supports optimal device drive current [T2]. The fundamental physical mechanism of this step relies on an ion-assisted chemical reaction within a high-density fluorocarbon plasma [P1]. Fluorine radicals from the plasma react with the SiO2 matrix to form volatile SiFx and COx byproducts, achieving vertical material removal [P1]. Simultaneously, the plasma generates fluorocarbon radicals (CFx) that deposit a carbon-rich polymer film on all exposed surfaces, creating a continuous competition between etching and passivation [P1]. The synergy between physical ion bombardment and chemical etching dictates the trench profile: energetic ions penetrate the polymer layer at the trench bottom to drive the SiO2 etch, while lower-energy ions on the sidewalls allow the polymer to accumulate and protect the lateral profile [P4]. Upon reaching the SiNx CESL, the etch chemistry exploits the intrinsically different surface reaction kinetics between SiO2 and SiNx to achieve high selectivity [P4]. On the SiO2 surface, liberated lattice oxygen helps volatilize the carbon as CO or CO2, keeping the passivating polymer mixing layer thin and easily penetrated by incident ions [P4]. Conversely, on the oxygen-free SiNx surface, a highly stable, thicker C-rich polymer layer forms, which severely suppresses fluorine penetration and drastically drops the etch rate [P4]. Fluorocarbon gases, such as CF4, C2F6, or CHF3, are selected as the primary etchants because their robust polymerizing capability is necessary to meet the dual requirements of high-aspect-ratio anisotropy and high material selectivity [P1]. To further enhance this SiO2-to-SiNx selectivity, diluent or polymer-modifying gases such as CH4 or H2 are commonly added to finely tune the plasma's carbon-to-fluorine (C/F) ratio [P1]. Increasing the C/F ratio promotes faster polymer deposition, which enhances the etch-stop capability on the CESL but must be carefully balanced against the risk of completely halting the SiO2 etch [P4]. Furthermore, maintaining lower process pressures and highly directional ion fluxes reduces ion scattering, which is critical for maintaining tight critical dimensions and suppressing sidewall physical damage [P2]. Independent control of ion energy and radical flux allows process engineers to modulate the reactive mixing layer thickness at the etch front, preventing excessive physical sputtering of the protective polymer [P4]. At the 40nm technology node for BSI CMOS Image Sensors, the physical constraints of dense pixel arrays make contact profile control and plasma damage mitigation exceptionally critical [P2]. The narrow contact diameters severely restrict the transport of volatile etch byproducts out of deep trenches, making plasma residence time a core parameter to prevent premature polymer pinch-off at the trench opening [P1]. Additionally, continuous exposure to the high-density plasma environment risks severe plasma charging damage (the antenna effect), where transient charging currents accumulate at the bottom of the contact trench [P3]. This unbalanced charge buildup can generate severe electrical damage to the adjacent gate oxides, leading to threshold voltage shifts and degraded gate-induced drain leakage (GIDL) [P3]. To avoid exacerbating the fundamental thermodynamic limits of subthreshold leakage [T1], ion energy must be tightly constrained below the threshold that causes extensive lattice dislocation in the surrounding semiconductor structures [P2].