40nm BSI CMOS Image SensorPreview

n the contact module [A2]. In the preceding steps, a Ti/TiN stack was deposited to line the contact trenches, where Ti serves to getter residual oxygen and lower the metal-semiconductor contact barrier, while TiN acts as a diffusion barrier preventing WF6 from reacting with the underlying structures during W chemical vapor deposition [P1]. The fundamental physics of the metal-semiconductor contact dictate that the barrier height is a function of the metal work function and semiconductor electron affinity, making the precise integration of the Ti/TiN liner critical for achieving low contact resistance [T1]. Following the bulk W removal, the residual TiN and Ti barrier layers remain on the field dielectric and must be completely removed to electrically isolate the individual W contact plugs [A2]. This step perfectly prepares the highly planarized surface required for the subsequent post-CMP cleaning and low-temperature anneal processes [P3]. The physical and chemical mechanism of TiN/Ti CMP operates on a coupled "chemical passivation–mechanical removal" sequence [P1]. In the slurry environment, oxidizers such as hydrogen peroxide (H2O2) drive electrochemical reactions on the Ti and TiN surfaces, forming nanoscale, softer passivation layers like TiOx [P1]. These passivation layers form at a rate governed by the material's corrosion potential, oxidation kinetics, and the slurry's chemical makeup [P1]. Subsequently, mechanical shear stress exerted by the polishing pad and abrasive particles continuously removes this oxidized film, exposing fresh underlying metal to repeat the cyclic removal process [P2]. The mechanical component of this material removal closely adheres to Preston's Equation, where the removal rate is directly proportional to the applied contact pressure and the relative velocity between the pad and the wafer [A1]. If the chemical passivation rate exceeds the mechanical removal rate, the process becomes mechanically limited, whereas the inverse results in a chemically limited regime [P1]. The primary objective during barrier CMP is to achieve high removal rate selectivity for Ti and TiN relative to the exposed W plugs and the underlying interlayer dielectric [P1]. Ex-situ electrochemical analysis demonstrates that increasing the oxidizer concentration accelerates the passivation rates of both Ti and TiN, enabling tunable removal rates [P1]. To prevent severe dishing of the already exposed W plugs during this barrier clearing phase, surface-active corrosion inhibitors are incorporated into the slurry to preferentially adsorb onto the W surface and moderate localized over-etching [A1]. Furthermore, the mechanical parameters must be carefully managed; applying excessive down-force increases the removal rate but significantly exacerbates oxide erosion in dense contact arrays [A1]. Strict control over the abrasive size distribution within the slurry is also mandatory, as abnormally large particles or agglomerates are the primary source of localized high contact stresses that generate severe surface defects [P4]. For a nanoscale back-illuminated (BSI) CMOS image sensor, the constraints on the TiN/Ti CMP process are exceptionally stringent due to the device's extreme sensitivity to noise and leakage [P3]. As contact plug dimensions shrink, the relative volume of tungsten decreases, elevating the baseline device resistance and making any CMP-induced W recess highly detrimental to performance [P1]. Additionally, residual metallic contaminants or trapped abrasive particles from the CMP process can create localized leakage paths or block subsequent patterning steps, severely degrading the pixel array's yield [P3]. Therefore, achieving global planarization without introducing micro-scratches or metallic residues is paramount for ensuring the integrity of the middle-of-line (MOL) interconnects [T2].