40nm BSI CMOS Image SensorPreview

ver, a thin layer of native oxide or residual pad oxide inevitably remains or regrows on the exposed silicon surface [P1]. To achieve low contact resistance, this interfacial oxide must be entirely removed prior to Ti/TiN deposition [T1]. This Pad Oxide Etch step prepares the pristine silicon surface necessary for reliable Ti silicide formation, which is a principal requirement for low-resistivity integrated contacts in the pixel area [P1]. Unlike bulk dielectric etches such as the PMD 5 Oxide Etch which define structural geometries, this specific step is a delicate interface preparation process designed exclusively to clear the metal-semiconductor boundary without consuming the underlying substrate [A2]. The core physical mechanism of this step relies on highly selective chemical dry etching rather than aggressive physical sputtering [P1]. Conventional Ar plasma sputtering can remove native oxide but induces severe lattice damage in the silicon, which degrades the contact resistance and yield [P1]. To avoid this, an in-situ dry chemical clean is utilized, wherein remote plasma generates reactive species like NH4F that selectively react with the SiO2 [P1]. This chemical reaction produces volatile or sublimable fluorosilicate salts, such as (NH4)2SiF6 [P1]. The silicon substrate is intrinsically protected because the chemical reaction is highly selective to the oxide and does not involve energetic ion bombardment of the silicon lattice [P1]. The salts are subsequently driven off the wafer surface through a thermally controlled sublimation process [P1]. The selection of a dry chemical etch over conventional wet cleans is dictated by the high aspect ratio of nanoscale contact holes, where surface tension limits the penetration and rinsing efficacy of aqueous solutions [P1]. By utilizing a gas-phase remote plasma process, the reactive species can uniformly reach the bottom of deep contacts (Engineering Practice). Process parameters such as reactant flow rates, plasma intensity, and precise wafer temperature control strictly dictate the reaction kinetics and the subsequent sublimation rate of the solid byproducts [P1]. Insufficient thermal energy during the sublimation phase leads to incomplete removal of the salt residues, which can physically block the subsequent Ti metallization and disrupt the formation of the low-resistance C54-TiSi2 phase [P1]. Conversely, careful optimization of the pre-etch time and temperature ensures optimal oxide removal while maintaining the structural integrity of the contact hole [P1]. At the 40nm node, the physical area available for the contact is significantly reduced, meaning that the interface properties dominate the total series resistance of the transistor [T1]. Any residual interfacial oxide acts as an insulating barrier, exponentially increasing resistance due to carrier tunneling limitations at the metal-semiconductor junction [T2]. For BSI CMOS image sensors, highly uniform and low-resistance direct Ti contacts are mandatory to prevent pixel-to-pixel electrical variations [P1]. Therefore, this targeted Pad Oxide Etch is critical for bridging the gap between deep-submicron geometric scaling and ideal carrier injection behavior [T3].