40nm BSI CMOS Image SensorPreview

D) and CESL 2 etches, and preceding the pad oxide etch and Ti barrier deposition [P2]. In advanced nodes like nanoscale, the Contact Etch Stop Layer (CESL) serves a dual purpose: acting as an etch stop during the thick PMD oxide etch to protect underlying structures [A1], and functioning as a process-induced strain layer to enhance carrier mobility in the MOSFET channel [P1]. The standard contact etch process typically opens vias through the PMD, stopping on the SiN CESL, followed by a dedicated CESL etch to expose the underlying active areas or gates [A1]. In a dual-stress liner integration scheme commonly used for mobility enhancement, CESL 1 and CESL 2 represent distinct SiN layers with different intrinsic stresses, such as tensile for NMOS and compressive for PMOS [P1, T2]. Etching CESL 1 specifically clears this bottom-most nitride layer at the bottom of the contact trench, preparing the surface for the subsequent pad oxide removal and silicide contact formation [P3]. The selective removal of the SiN CESL is achieved via plasma etching, a process relying on the synergistic interaction between ion bombardment and chemical radicals [P3]. For SiNx etch stop layers, hydrofluorocarbon-based gas mixtures, specifically CH3F or CH2F2, are typically employed to achieve high selectivity against the surrounding SiO2 PMD and the underlying silicide or pad oxide [P3]. The core mechanism heavily depends on the formation of a protective fluorocarbon polymer film; the hydrogen in these gases scavenges fluorine to form HF, creating a carbon-rich polymer that selectively deposits on the oxide sidewalls and the underlying silicon/silicide, while directional ion bombardment clears it from the nitride surface to allow continuous etching [P3]. This delicate balance between polymer deposition and physical sputtering is governed by Langmuir-Hinshelwood-type surface kinetics, where the etch rate is controlled by the adsorption coverage of neutral radicals and the directional kinetic energy of incoming ions [P3]. The use of a highly selective, "soft" plasma etch is critical because excessive exposure of the underlying silicided source and drain to ion bombardment can lead to junction degradation and increased series resistance [P3, T1]. Because the CESL film possesses high intrinsic stress—ranging from +1.6 GPa to -3.0 GPa depending on deposition conditions [P1]—its structural density and bonding configuration (a-SixNyHz) can influence the local etch rate (Engineering Practice). Process parameters such as RF power, chamber pressure, and gas flow ratios must be tightly controlled to modulate ion energy and radical flux, thereby minimizing physical damage to the shallow junctions typical of advanced devices [P3, T2]. Furthermore, Aspect Ratio Dependent Etching (ARDE) must be strictly managed, as the variation in contact depths between the gate and the source/drain regions necessitates an etch process that can clear all contacts simultaneously without aggressive overetching [P3]. At the 40nm node, managing the physical trade-off between transistor drive current (Ion) and subthreshold leakage (Ioff) is paramount [T2]. Since device scaling limits geometric performance gains, the highly stressed PECVD SiN CESL is essential for altering the silicon lattice constant and carrier effective mass, thereby increasing mobility by up to 10% [P1]. Consequently, the CESL 1 Etch must preserve the structural integrity and mechanical stress of the surrounding liner while selectively opening the contact via [P1]. The distinction between CESL 1 and CESL 2 etches in the flow implies a sequential removal of differently stressed or deposited layers, requiring the etch chemistry to be finely tuned to the specific hydrogen content and density of the CESL 1 film to avoid profile bowing or punch-through [P1, P3].