40nm BSI CMOS Image SensorPreview

llowing the initial photoresist patterning and upper dielectric breakthrough in the preceding PMD 4 Etch, this step continues the anisotropic pattern transfer deep into the pre-metal dielectric stack (Engineering Practice). This vertical etching sequence ultimately prepares the physical pathway for metallic vias and local interconnects to physically and electrically couple the transistor gate and source/drain regions [A1]. A sequential, multi-step etch strategy is employed to manage the differing etch selectivities of a complex dielectric stack, preventing profile bowing or micro-trenching before reaching the Contact Etch Stop Layer (CESL) [P2]. Ensuring a highly vertical and clean profile during this intermediate phase is mathematically and physically essential for the subsequent metallization to achieve a low specific contact resistance, which relies heavily on forming an unperturbed metal-semiconductor interface [T2]. This etch operates via Reactive Ion Etching (RIE), a process that relies on the synergistic action of surface chemical reactions and physical ion bombardment [P1]. Neutral radicals generated in the low-pressure plasma dominate the chemical reaction, forming volatile byproducts with the exposed dielectric matrix [P2]. Simultaneously, positively charged ions are accelerated across the plasma sheath by an applied RF bias voltage, gaining highly directional kinetic energy [P1]. This directed ion bombardment preferentially clears the fluorocarbon polymer deposited on the horizontal bottom of the trench, allowing the chemical etch to proceed vertically while the polymer protects the sidewalls from lateral etching [P2]. Maintaining this dynamic equilibrium between chemical etching and oxidative or polymeric passivation is fundamental to achieving high selectivity and verticality, following the identical physical competition mechanisms utilized in selective compound semiconductor etching [P4]. Fluorocarbon-based gas chemistries are typically selected because they naturally provide the necessary polymerizing precursors required for sidewall passivation during continuous deep dielectric etching [P2]. Process parameters such as RF power, chamber pressure, and gas ratios interact comprehensively to dictate the ratio of chemical etchants to physical sputtering agents [P2]. Higher ion energies artificially increase the physical sputtering component, driving the etch deeper into the HARC structure but elevating the risk of kinetic lattice damage [P1]. Conversely, increasing the polymerizing gas ratio enhances sidewall protection but risks etch stop if the local polymerization rate exceeds the ion clearing rate at the trench bottom [P1]. Furthermore, precise control of the bias voltage is strictly maintained to minimize transient plasma charging currents, which could otherwise degrade the gate dielectric through localized charge accumulation [P3]. At the 40nm node for Backside Illuminated (BSI) CMOS Image Sensors, strict control over plasma-induced damage is paramount because unmitigated lattice defects generate mid-gap trap states that severely degrade sensor performance [P1]. These process-induced trap states act as generation-recombination centers, directly contributing to elevated dark current and white pixel defects in the active photodiode array [P1]. Additionally, as device dimensions scale down and integration density increases, the aspect ratio of the contacts increases drastically, exacerbating the antenna effect where transient charging currents degrade the subthreshold swing and threshold voltage of the transistors [P3]. Therefore, the PMD 3 Etch must employ highly collimated ion delivery to mitigate localized charge accumulation while ensuring efficient dielectric removal [P1].