CESL 2 - Etch - 40nm BSI CMOS Image Sensor 40nm

If the radical flux is too high, the polymer layer thickens excessively, exponentially reducing the etch rate and leading to a complete etch stop condition .

The CESL 2 - Etch step occurs immediately after the bulk Pre-Metal Dielectric (PMD) oxide has been anisotropically etched to open the conta

ct holes . In the 40nm BSI CMOS Image Sensor flow, the contact module utilizes a multi-layer Contact Etch Stop Layer (CESL) scheme to provide both robust etch stopping capabilities and highly localized channel strain . Because the preceding PMD etching processes use high-selectivity fluorocarbon plasmas designed to stop efficiently on the uppermost nitride layer, this specific step is required to break through the upper CESL (CESL 2) before a separate step handles the lower CESL (CESL 1) . This sequential multi-step etching ensures that the underlying silicide and epitaxial source/drain regions are not exposed prematurely, thereby protecting the sensitive active areas from severe over-etching damage during the deep PMD clearance . The etching of the amorphous hydrogenated silicon nitride (a-SixNyHz) CESL relies on reactive ion etching (RIE) utilizing a carefully balanced fluorocarbon plasma . The fundamental mechanism involves the continuous deposition of a fluorocarbon (CF) polymer film on the nitride surface, coupled with simultaneous physical ion bombardment that drives the chemical removal of the material . Unlike silicon dioxide, which releases oxygen during etching to volatilize the polymer, silicon nitride lacks an internal oxygen source, causing the CF film to grow thicker and dissipate incident ion energy . To sustain the etch process without stopping, the reactive species flux—particularly the CFx radicals—must be precisely tuned against the ion energy to penetrate the steady-state polymer layer . The reaction ultimately forms volatile fluorinated byproducts, clearing the CESL 2 layer strictly within the defined geometric boundaries of the contact hole (Engineering Practice). A highly directional, anisotropic dry etch method is selected for this step to maintain the critical dimensions of the high-aspect-ratio contact holes defined during the PMD etch . The plasma chemistry parameters, such as the ratio of polymerizing gases to inert carriers and trace oxidants, are dynamically adjusted to modulate the transient CF polymer thickness . If the radical flux is too high, the polymer layer thickens excessively, exponentially reducing the etch rate and leading to a complete etch stop condition . Conversely, inadequate polymer formation degrades the etch selectivity to the underlying CESL 1 layer or adjacent spacer structures, leading to uncontrolled profile bowing or spacer erosion . Furthermore, the choice of process pressure and radio-frequency (RF) bias voltage directly dictates the mean free path and the perpendicular electric field, which physically govern the trajectory and energy of the bombarding ions (Engineering Practice). In the 40nm node, continuous geometrical scaling drastically reduces the available contact area, which inversely increases the intrinsic contact resistance . Therefore, the CESL 2 etch must be executed with minimal lateral isotropic etching to prevent the enlargement of the contact critical dimension (CD), which could easily cause fatal electrical shorts between the contact metal and the adjacent metal gate . Because the PECVD SiN CESL acts as a primary source of mechanical strain to physically alter the silicon lattice constant and enhance channel carrier mobility, preserving the structural integrity of the unetched film surrounding the contact hole is paramount . The dual-CESL step sequence allows the plasma parameters to be sequentially stepped down in chemical aggressiveness, ensuring that the final contact interface—which may utilize specialized sloped or recessed profiles to maximize electrical contact area—remains free of plasma-induced crystalline damage .

[High] Incomplete CESL 2 Clearance (Etch Stop): If the CFx radical flux in the plasma is excessively high relative to the incident ion bombardment energy, a thick fluorocarbon polymer film accumulates on the silicon nitride surface, dissipating the ion energy and completely halting the etch process . This prevents the subsequent CESL 1 etch from reaching the active area, ultimately leading to an open circuit or catastrophically high contact resistance .
[Medium] Lateral CD Blowout and Spacer Erosion: If the plasma chemistry lacks sufficient polymerizing precursors to adequately passivate the sidewalls during the etch, the contact hole critical dimension can expand laterally . This isotropic erosion can aggressively consume the protective dielectric spacers on the gate, potentially exposing the gate conductor and causing a direct gate-to-contact short .
[Medium] Substrate Damage from Premature Punch-Through: Although this specific step targets only CESL 2, poor etch selectivity or excessive RF bias can cause the plasma to punch through CESL 1 prematurely . High-energy ion bombardment would then directly strike the underlying silicon or silicide interface, inducing sub-surface lattice defects that disrupt carrier transport and degrade the transistor's subthreshold swing .
[Low] Transistor Channel Strain Relaxation: The CESL film is explicitly deposited with high intrinsic stress to elastically deform the silicon lattice and improve carrier effective mass and mobility . Severe over-etching or excessive plasma heating of the CESL film surrounding the contact hole can cause localized mechanical decoupling, reducing the induced strain in the channel and directly degrading the transistor drive current .

If the radical flux is too high, the polymer layer thickens excessively, exponentially reducing the etch rate and leading to a complete etch stop condition .

The CESL 2 - Etch step occurs immediately after the bulk Pre-Metal Dielectric (PMD) oxide has been anisotropically etched to open the conta

[High] Incomplete CESL 2 Clearance (Etch Stop): If the CFx radical flux in the plasma is excessively high relative to the incident ion bombardment energy, a thick fluorocarbon polymer film accumulates on the silicon nitride surface, dissipating the ion energy and completely halting the etch process . This prevents the subsequent CESL 1 etch from reaching the active area, ultimately leading to an open circuit or catastrophically high contact resistance .
[Medium] Lateral CD Blowout and Spacer Erosion: If the plasma chemistry lacks sufficient polymerizing precursors to adequately passivate the sidewalls during the etch, the contact hole critical dimension can expand laterally . This isotropic erosion can aggressively consume the protective dielectric spacers on the gate, potentially exposing the gate conductor and causing a direct gate-to-contact short .
[Medium] Substrate Damage from Premature Punch-Through: Although this specific step targets only CESL 2, poor etch selectivity or excessive RF bias can cause the plasma to punch through CESL 1 prematurely . High-energy ion bombardment would then directly strike the underlying silicon or silicide interface, inducing sub-surface lattice defects that disrupt carrier transport and degrade the transistor's subthreshold swing .
[Low] Transistor Channel Strain Relaxation: The CESL film is explicitly deposited with high intrinsic stress to elastically deform the silicon lattice and improve carrier effective mass and mobility . Severe over-etching or excessive plasma heating of the CESL film surrounding the contact hole can cause localized mechanical decoupling, reducing the induced strain in the channel and directly degrading the transistor drive current .

40nm BSI CMOS Image SensorPreview

Process Cross-Section

Step highlight

In depth

Risks & Challenges

40nm BSI CMOS Image SensorPreview

Process Cross-Section

Step highlight

In depth

Risks & Challenges