40nm BSI CMOS Image SensorPreview

ce at the bottom is exposed [P1]. The Ti deposition step is the critical first stage of the middle-of-the-line (MOL) contact plug metallization [P1]. Ti serves as an adhesion layer and an oxygen-scavenging agent that prepares the contact bottom for subsequent barrier formation [P2]. In the process flow, it directly precedes the TiN diffusion barrier and the chemical vapor deposition (CVD) of tungsten (W) [P1]. By establishing a direct metallic interface with the underlying silicon or pre-formed silicide, the Ti layer ensures the structural integrity and electrical continuity required for low-resistance signal routing [P2]. The primary mechanism of Ti deposition is to facilitate the formation of a low-resistance ohmic contact by lowering the effective interface barrier [T2]. At the nanoscale, metal resistivity and contact resistance are strongly influenced by interface scattering and parallel/series thin-layer structures [P2]. Titanium is uniquely suited for this because it can getter residual oxygen and react with silicon during subsequent thermal cycles to form highly conductive titanium silicide [P2]. This localized silicide formation creates a highly conductive path, bypassing any thin native oxide that might have re-formed after the pre-clean step (Engineering Practice). Furthermore, the deposition physics in high-aspect-ratio contacts relies on ionized metal plasma (IMP), where metal atoms are ionized and accelerated by an electric field to gain directional kinetic energy [P1]. This electric field-driven transport significantly enhances the flux of Ti ions reaching the bottom of the contact hole, ensuring adequate coverage where traditional line-of-sight physical vapor deposition (PVD) would suffer from severe shadowing effects [P1]. The selection of IMP Ti over standard PVD is driven by the strict geometric constraints of advanced logic and sensor contact holes [P1]. As contact dimensions shrink, securing sufficient bottom coverage without choking the hole opening becomes a fundamental transport challenge [P4]. The critical parameters during IMP deposition include the RF power, which controls the ionization rate, and the substrate bias, which dictates the arrival energy and directionality of the Ti ions [P1]. There is a delicate balance in tuning these parameters: excessive Ti thickness or overly aggressive ion bombardment can cause physical damage to the shallow junction below, leading to stress concentration and a steep increase in junction leakage [P1]. Conversely, insufficient Ti deposition results in incomplete silicide formation and high contact resistance [P1]. For a nanoscale Backside Illuminated (BSI) CMOS Image Sensor, maintaining pristine junction integrity is paramount because any stress or metal-induced defect directly translates to elevated dark current and white pixel defects (Engineering Practice). The optimization of the Ti adhesion layer must therefore carefully balance the competing relationships among interface damage, bottom coverage, contact resistance, and junction leakage [P1]. Minimizing the Ti layer thickness while maintaining a continuous film is essential to prevent junction punch-through in the highly scaled source/drain regions characteristic of the 40nm node [P1].