Consequently, the seed layer here must support larger-volume Cu electroplating while ensuring exceptional electromigration resistance for high current densities .
In depth
In the Damascene approach for state-of-the-art ultra-large-scale integrated (ULSI) devices, copper is deposited by electrochemical dep
osition (ECD) into patterned dielectrics . However, ECD requires a continuous metallic nucleation layer over the diffusion barrier to initiate uniform plating and provide a conductive path . Following the deposition of the Ta-based liner in the MET6 module, this step establishes the requisite conductive Cu foundation . Unlike lower-level metals, MET6 in a 40nm BSI CMOS Image Sensor typically serves as a thicker power-routing layer or a top-level interconnect (Engineering Practice). Consequently, the seed layer here must support larger-volume Cu electroplating while ensuring exceptional electromigration resistance for high current densities . Traditional Physical Vapor Deposition (PVD) utilizes an ionized argon plasma to sputter Cu atoms from a target onto the wafer . To optimize coverage inside features, modern processes employ a moderate wafer bias to establish a balance between ion bombardment and neutral Cu deposition . This bias directs the Cu ions vertically into the trench, forming a continuous layer at the bottoms and sidewalls . However, in highly scaled structures, the seed layer may become discontinuous, forcing electrodeposited Cu to nucleate as isolated particulate islands rather than a smooth, continuous film . To mitigate this, advanced deposition techniques may integrate a thermal reflow step where surface energy and chemical potential gradients drive Cu atom migration along the sidewalls, effectively pre-filling the feature and reducing the effective aspect ratio . Pure Cu is the standard seed material due to its compatibility with the bulk ECD Cu, acting as a critical electronic transport and nucleation layer . To enhance long-term interconnect reliability, the seed layer may be alloyed with trace impurities such as manganese, aluminum, or tin . During subsequent thermal processing or capping layer deposition, these impurities diffuse and segregate to grain boundaries or interfaces, significantly reducing the grain-boundary diffusion rates of copper atoms . This segregation mechanism fundamentally suppresses electromigration, which is governed by the Arrhenius diffusion equation where the activation energy for atom movement is effectively increased . Process parameters such as sputtering power, wafer bias, and substrate temperature must be carefully co-optimized; excessive bias can cause resputtering of the underlying Ta liner, while insufficient temperature inhibits the surface mobility necessary for uniform coverage . At the 40nm node, while MET6 dimensions are more relaxed than local interconnects, the cumulative thermal budget and structural integrity demands remain stringent (Engineering Practice). The choice of an optimized Cu seed process here ensures that the subsequent high-volume electroplating does not form sidewall or line-top voids, guaranteeing robust device yield .
Risks & Challenges
[High] Discontinuous Seed Coverage: If the Cu seed is too thin or discontinuous on sidewalls, subsequent electrodeposition current density concentrates locally, causing preferential growth at isolated islands and resulting in severe voiding .
[Medium] Ta Liner Resputtering: Application of an excessively high wafer bias during PVD deposition can lead to energetic Cu ions bombarding and etching away the underlying Ta-based barrier, thereby compromising diffusion resistance .
[Medium] Seed Oxidation (Queue Time Failure): Increasing the queue time between seed deposition and electroplating allows ambient surface oxidation of the thin Cu layer, which degrades effective nucleation density and produces coarser, separated deposits .
[Low] Excessive Field Deposition (Overhang): A suboptimal balance of neutral deposition and ion bombardment can cause excessive Cu accumulation at the trench openings, creating an overhang that pinches off the feature prior to complete bottom-up fill .