40nm BSI CMOS Image SensorPreview

A2]. Following the deposition of a Ta-based barrier and a copper seed layer, this step completely fills the high-aspect-ratio V5 vias and M5 trenches with bulk copper before the subsequent chemical mechanical planarization (CMP) step [P3]. Copper is utilized as the interconnect material because its low electrical resistance and high allowable current density help mitigate severe resistive-capacitive (RC) delays in scaled integrated circuits [P2]. As transistor dimensions shrink and drive currents increase to improve switching speeds [T2], the interconnect vias face significant resistance increases due to size effects [A1]. Unlike lower metal layers (M1 to M4) that are primarily optimized for ultra-tight pitch local routing, M5 in a 40nm BSI CMOS Image Sensor often serves as a thicker, lower-resistance layer for power distribution or optical shielding, necessitating highly robust bulk filling [T2]. The physical operation of this step relies on an electrochemical deposition (ECD) process driven by a time-dependent "bottom-up" fill mechanism [P1]. This mechanism is governed by the synergistic interaction of multiple organic additives within the plating bath, typically comprising an inhibitor (such as polyethylene glycol, PEG), an accelerator (such as bis(3-sulfopropyl) disulfide, SPS), and stabilizing chloride ions [P1]. When the wafer is immersed and current is applied, transient diffusion and surface adsorption kinetics dominate the initial phase [P3]. PEG strongly adsorbs to the exposed copper surfaces, but its diffusion into high-aspect-ratio features is extremely slow due to its rapid adsorption and consumption on the upper sidewalls [P1]. Conversely, the accelerator SPS diffuses faster into the via and exhibits slower adsorption kinetics, allowing it to gradually displace the weakly bound PEG at the via bottom [P1]. This spatial disparity creates a dynamically evolving surface coverage where the inhibitor suppresses plating at the top, while the accelerator enriches at the bottom, triggering a significantly higher local deposition rate that enables void-free filling [P3]. Electrochemical deposition is selected over physical or chemical vapor deposition because it is uniquely capable of providing rapid, defect-free filling of high-aspect-ratio structures near room temperature [P3]. The success of this process is strictly controlled by tuning parameters such as applied current density, bath temperature, and the relative concentrations of additives, which jointly determine the transient diffusion fluxes and adsorption time constants [P1]. Pulse plating modes may also be utilized to control instantaneous overpotentials and minimize localized side reactions, ensuring high-density nucleation [P4]. Following deposition, the copper film typically undergoes a thermal annealing step to drive grain growth and reduce internal scattering [A2]. In advanced metallization schemes, thermal annealing can also be used to drive specific dopants toward the copper-barrier interface, forming a segregated layer that significantly suppresses atomic migration pathways and improves long-term electromigration reliability [A2]. For 40nm technology, the scaling of the trench and via dimensions fundamentally challenges the integrity of the prior thin copper seed layer [A2]. Conventional highly acidic plating baths can cause rapid corrosion and dissolution of extremely thin copper seeds upon immersion [P4]. Therefore, the M5 Cu ECD process must be engineered to initiate immediate transient bottom-up growth within seconds, minimizing the duration the interface spends in an unsteady state before complete copper coverage is achieved [P1].