40nm BSI CMOS Image SensorPreview

interconnect material due to its low electrical resistivity and high electromigration resistance [P1]. However, copper is a highly reactive metal and a fast diffuser in silicon and dielectrics, where its presence can create deep trap levels that severely degrade device performance [P2]. To prevent this degradation, the Ta-based liner deposition step acts as a critical diffusion barrier [P1]. Situated immediately after the ILD trench/via etch and clean, this step lines the exposed dielectric surfaces prior to the Cu seed deposition and bulk electroplating [A1]. Unlike similar Ta-based depositions at lower metal levels (e.g. [P2], steps 155, 171, 187) which prioritize ultra-thin scaling for fine-pitch routing, this MET6 deposition is optimized for the larger geometries, higher current-carrying capacities, and specific aspect ratios typical of upper-level routing in a 40nm BSI CMOS Image Sensor [T2]. The physical mechanism of this barrier layer relies on the high melting point, thermodynamic stability, and dense crystalline or amorphous structure of tantalum and its nitrides, which fundamentally block copper diffusion along grain boundaries [P2]. When employing plasma-enhanced atomic layer deposition (PEALD), a metal-organic precursor such as TAIMATA or a halide like TaCl5 undergoes saturated adsorption onto the dielectric surface, forming a self-limiting monolayer [P4]. Subsequently, a hydrogen plasma pulse generates highly reactive hydrogen radicals that break the precursor ligand bonds, removing residual alkyl or halogen groups and forming dense metal-nitrogen or metal-metal bonds [P1]. This non-thermal energy from the plasma enables the reduction reactions to occur at low temperatures (e.g. [P2], below 400°C), which is strictly required to preserve the structural integrity of the underlying low-k dielectrics [P4]. A bilayer system consisting of TaN and Ta is often preferred: TaN provides exceptional barrier properties against dielectrics, while pure Ta or carbon-doped Ta(C)N offers superior interfacial adhesion to the subsequent copper seed [P1]. The process parameters, particularly hydrogen plasma time and power, dictate the chemical and crystallographic outcome [P1]. High plasma power increases ion bombardment energy, which drives atomic surface rearrangement and promotes the formation of a low-resistivity cubic TaN phase rather than a highly resistive Ta3N5 phase [P1]. Furthermore, optimized plasma exposure induces a preferred (200) crystallographic orientation, which minimizes the lattice mismatch with the (111) orientation of the subsequent copper seed layer [P1]. This structural alignment lowers interfacial strain and significantly improves copper adhesion without requiring an intermediate glue layer like ruthenium [P1]. At the 40nm node, the continued geometric scaling of integrated circuits mandates that the diffusion barrier be ultra-thin to maximize the volume available for copper fill [P3]. If the Ta-based liner consumes too much of the cross-sectional area of the trench or via, the effective interconnect resistivity increases drastically, undermining device speed [P3]. Additionally, as feature sizes shrink and aspect ratios increase, conventional physical vapor deposition (PVD) suffers from line-of-sight limitations, leading to poor conformality [P2]. The self-limiting reaction kinetics of ALD-based processes overcome this limitation, ensuring continuous atomic-scale thickness control on vertical sidewalls and via bottoms [P4]. This uniform coverage prevents localized barrier thinning and ensures robust protection against copper diffusion under high electromigration stress conditions [A1].