Strip and cleaning removes residual polymers and contaminants from the low-k trench surface to ensure uniform metal deposition and prevent electrical shorts .
The strip and cleaning step follows MET6 trench ashing to prepare the low-k dielectric trench for Ta-based liner and Cu seed deposition [
P3]. Ashing primarily removes the bulk organic photoresist, but it often leaves behind highly crosslinked fluorocarbon polymer residues generated during the preceding fluorocarbon-based dielectric etch . If these post-etch residues remain on the trench sidewalls, they severely degrade the adhesion of the subsequent Ta barrier layer and increase contact resistance at the via bottom . Therefore, this wet cleaning step is mandatory to achieve a pristine surface, ensuring the structural integrity and electrical performance of the Cu interconnects . The cleaning mechanism relies on a combination of chemical dissolution and structural modification to detach firmly adhered polymeric and organometallic residues . Fluorocarbon polymers formed during plasma etching create a dense, C-F rich network that conventional organic solvents struggle to penetrate . To overcome this, advanced stripping formulations utilize specific solvent chemistries or oxidizing aqueous compositions that chemically break down the residue . In some integration schemes, UV irradiation is introduced prior to or during cleaning to induce photochemical chain scission of C-C and C-F bonds, reducing the crosslink density of the polymer backbone and introducing polar groups to enhance solvent wetting . Oxidizing agents in the cleaning solution, such as ammonium salts, can also be employed to dissolve metallic residues, while corrosion inhibitors like primary alkylamines selectively adsorb onto exposed metals to prevent unwanted etching . The selection of cleaning chemistry must balance high residue removal efficiency with strict compatibility with ultra-low-k (ULK) dielectrics and exposed interconnect materials . Aqueous or semi-aqueous mixtures containing organic solvents, buffering agents, and metal chelators are often chosen to complex dissolved metal ions and prevent their redeposition on the wafer surface . However, because low-k dielectrics rely on nanoporosity to reduce the interconnect capacitance, they are highly susceptible to moisture and chemical penetration . If the molecular size of the cleaning solvent or water is smaller than the interconnected pores of the dielectric, the fluid will permeate the film, causing an unwanted increase in the k-value and degrading the diffusion barrier properties . Therefore, process parameters such as chemical concentration, bath temperature, and immersion time must be tightly controlled to maximize cleaning yield without inducing dielectric degradation or metal interconnect corrosion . In 40nm BSI CMOS image sensors, the aggressive scaling of BEOL interconnects exacerbates the trade-off between residue removal and dielectric preservation . As trench dimensions shrink, capillary forces within the narrow trenches make chemical transport and byproduct evacuation increasingly difficult (Engineering Practice). Furthermore, the reduced mechanical strength and higher porosity of the low-k materials used at this node make them exceptionally vulnerable to chemical attack during wet cleaning . The integration of complex 3D structures, such as deep vias for front-to-backside signal routing, further demands highly selective and penetrative cleaning processes to ensure defect-free metallization .
Sign in to continue through all 417 steps