40nm BSI CMOS Image SensorPreview

ILD 5-1 SiCN Etch

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Ashing & Strip/Clean

METAL 6 TRENCH - Photo
216METAL 5 TRENCH - Photo217ILD 4-2 Oxide Etch218Ashing & Strip/Clean219Ta-based liner deposition220Cu Seed deposition221Metal 4 Cu deposition222Cu CMP223Ta-based liner CMP224Post CMP Cleaning225ILD 5-1 Deposition226ILD 5-2 Deposition227Pre Litho Cleaning228VIA 5 - Photo229ILD 5-2 Oxide Etch230ILD 5-1 SiCN Etch231Ashing & Strip/Clean

Process Cross-Section

V5 · Ashing & Strip/Clean (via open)IO/HV gate ox (SiO2; relative thickness shown schematically; IO device not shown in this cross-section)TiSi (low-temp anneal)n- LDD (31P+, self-aligned)P-pinning (11B+)P+ VSS contact (11B+)FD node (31P+)VT adjust (11B+, periphery channel)SiO2 liner (SACVD)SiO2 (SACVD bulk fill)n+ S/D (31P+)n+ N-well contact (31P+)p+ surface passivation (10B+)Liner SiO2 (RTP thermal)P-well (pixel array, 11B+)P-well (periphery, 11B+)PD N-well (31P+)N-well (periphery, 31P+)SiP-well (implanted region)SiO2CESLCuTaPMD 5 (SiO2)PMD 4 (SiO2)MET0 (W)PMD 3 (SiO2 · CMP overburden)W (contact fill)PMD 2 (SiO2 · body segment)TiN (barrier)Ti (adhesion)Ti/TiN linerPMD 1 (SiO2 · bottom segment)CESL 2 (SiNO)SiNCESL 1 (SiN)PolySWS pad ox (SiO2, PECVD)gate ox (SiO2, thermal)

Step highlight

The wet stripping composition typically includes organic solvents paired with specific corrosion inhibitors, such as long-chain primary alkylamines, which selectively adsorb onto the exposed M5 copper to prevent its dissolution .

In depth

Following the ILD 5-1 SiCN Etch, the underlying M5 copper interconn

ect is physically exposed at the bottom of the via (Engineering Practice). During this upstream anisotropic etch, fluorocarbon-containing plasmas deliberately deposit highly crosslinked fluoropolymer (CFx) residues on the dielectric sidewalls to maintain profile control and etching anisotropy . However, these residues, along with any remaining heavily crosslinked photoresist, must be completely removed to ensure high adhesion and good coverage for the subsequent barrier metal deposition . If left uncleaned, the insulating polymer network physically blocks the electrical connection to the underlying copper, resulting in catastrophic via open failures or elevated contact resistance . Compared to earlier lower-level via cleans, this V5 step handles deeper, higher-aspect-ratio structures that interface directly with upper-level global routing copper, necessitating highly efficient residue extraction without oxidizing the exposed metal . The physical and chemical mechanism of this step relies on overcoming the chemical inertness of the post-etch residues while preventing damage to the porous low-k dielectric . Conventional high-temperature oxygen plasma ashing causes severe damage to porous low-k materials by abstracting carbon-based groups, extending damage underneath hard mask edges, and producing non-planar top surfaces that lead to interline capacitance issues . To mitigate this, advanced processes employ structural modification of the polymer followed by wet chemical dissolution . Ultraviolet (UV) irradiation (e.g. (Engineering Practice), nanoscale) can be utilized to induce photochemical chain scission in the polymer backbone, breaking C-C and C-F bonds to significantly reduce the crosslink density and molecular weight . Alternatively, dissolved ozone can be introduced to selectively oxidize and cleave C=C unsaturated bonds within the plasma-hardened resist shell . Once the polymer structure is weakened, organic solvents penetrate the dense network, while megasonic acoustic waves generate liquid cavitation and microjets to enhance mass transport and physically delaminate the residues from the high-aspect-ratio sidewalls . Material and method selections are strictly governed by the dual need for cleaning efficiency and interconnect compatibility . The wet stripping composition typically includes organic solvents paired with specific corrosion inhibitors, such as long-chain primary alkylamines, which selectively adsorb onto the exposed M5 copper to prevent its dissolution . If oxidizers are incorporated to break down stubborn residues or residual hardmask components, their concentration and the solution pH must be carefully balanced to prevent the oxidation of the metal lines . From a parameter interaction perspective, increasing megasonic power and solvent temperature accelerates the dissolution kinetics of the photoresist and bottom anti-reflective coating (BARC) . However, higher temperatures and acoustic intensities also promote the ingress of polar solvents into the pores of the low-k dielectric, which artificially increases its dielectric constant . Consequently, the wet cleaning process is intrinsically coupled with a subsequent low-pressure bake step designed to drive out residual solvent and fully restore the electrical properties of the low-k film . At the 40nm node, shrinking critical dimensions (CD) impose severe constraints on the process window for post-etch residue removal . In previous technology generations, slight dielectric under-etching using dilute aqueous hydrofluoric acid (HF) could be employed to lift off polymers, but at nanoscale, such CD loss is completely unacceptable [P1, P3]. Furthermore, complex integration schemes generate highly crosslinked resist crusts that are immune to standard chemical dissolution . High-temperature thermal ashing also risks hardening the photoresist further, transforming it into a carbon-rich polymeric crust that standard wet cleans cannot attack . Therefore, integrating low-damage modification techniques—such as UV pretreatment or in-situ low-temperature plasma—with highly selective, cavitation-assisted wet chemistry is a strict requirement to maintain CD fidelity and achieve defect-free copper interfaces in nanoscale BEOL processing [P2, P4].

Risks & Challenges

  • [High] Low-k Dielectric Degradation (k-value shift): Prolonged exposure to plasma ashing or polar wet solvents strips hydrophobic carbon-based groups from the porous low-k matrix or allows solvent ingress into the pores . This dramatically increases the dielectric constant, leading to elevated interline capacitance, RC delay, and potential dielectric breakdown .
  • [High] Copper Corrosion at Via Bottom: If the wet cleaning formulation contains excessive oxidizing agents (such as ammonium salts) or lacks sufficient selectively adsorbing corrosion inhibitors, it will chemically attack the exposed M5 copper . This leads to copper pitting and recess, which degrades the interface contact area and accelerates electromigration failure .
  • [Medium] Incomplete Fluorocarbon Residue Removal: If the UV dose is insufficient to cause adequate polymer chain scission, or if megasonic energy fails to penetrate the deep V5 structures, the highly crosslinked CFx residues will remain firmly attached to the sidewalls [P1, P2]. This creates a physical barrier that prevents proper barrier metal adhesion, leading to high via resistance or void formation during metallization .
  • [Medium] Plasma-Induced Resist Hardening: If the preceding dry strip utilizes excessively high temperatures during O2 ashing, thermochemical reactions cause the photoresist to severely crosslink and harden . This produces a carbon-rich polymeric crust that becomes highly resistant to subsequent wet dissolution, leaving defect islands that block subsequent processing steps .
  • [Low] Incomplete Solvent Outgassing: Solvents used to dissolve post-etch residues can remain trapped in the low-k porous network if the post-clean bake temperature or vacuum level is inadequate . Trapped solvent reduces the breakdown voltage of the dielectric and can cause outgassing-induced voids in the subsequent barrier/seed layers .

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Related steps

  • VIA 5 - Photo
  • ILD 5-2 Oxide Etch
  • ILD 5-1 SiCN Etch
  • Strip & Cleaning