corrosion inhibitors, such as long-chain primary alkylamines, are integrated into the chemistry to selectively adsorb onto exposed underlying metals, preventing oxidative corrosion .
Following the ILD 4-2 Oxide Etch, the wafer contains patterned Metal 5 trenches filled with bulk post-etch photore
sist, bottom anti-reflective coating (BARC) residues, and fluorocarbon-based polymeric sidewall passivants . The purpose of this Ashing & Strip/Clean step is to completely remove these organic masks and plasma-induced residues without degrading the underlying porous low-k inter-layer dielectric (ILD) . This operation prepares a pristine, defect-free dielectric cavity essential for the subsequent conformal deposition of the Ta-based barrier liner and copper seed layer . Unlike lower-level front-end cleans that handle robust silicon oxides, this MET5 step deals specifically with ultra-low-k (ULK) organosilicate materials, making the balance between aggressive residue removal and dielectric preservation critically distinct . The physical and chemical mechanism of this step relies on a delicate sequence of radical volatilization and solvent dissolution (Engineering Practice). To avoid severe plasma-induced damage, traditional oxygen (O2) plasma ashing is largely replaced by reducing chemistries, such as H2-based or H2O-vapor plasmas, which minimize the stripping of protective methyl (Si-CH3) bonds from the low-k matrix [P3, P4]. Following the dry ash, a highly specialized wet cleaning chemistry is applied to dissolve the remaining highly cross-linked organometallic crusts and fluorocarbon (CFx) polymers . The solvent system penetrates the residue networks, disrupting interfacial adhesion through chemical complexation and selective solvation of functional groups like esters and lactones . In advanced methodologies, ultraviolet (UV) irradiation at nanoscale may precede the wet clean to photochemically cleave C-C and C-F bonds in the fluoropolymer backbone, significantly enhancing solvent wetting and removal efficiency . Material and parameter selection for the stripping chemistry is strictly dictated by the dual requirement of high residue solubility and low-k compatibility . Wet formulations often incorporate specific water-soluble organic solvents, alkaline components, and sometimes trace metal ions to modulate interfacial surface tension and suppress chemical attack on the porous ILD . To overcome mass transport limitations within the high-aspect-ratio nanoscale trenches, megasonic agitation is frequently applied to generate cavitation and microjets, accelerating dissolution kinetics at the residue-substrate interface . Furthermore, corrosion inhibitors, such as long-chain primary alkylamines, are integrated into the chemistry to selectively adsorb onto exposed underlying metals, preventing oxidative corrosion . Post-clean, a low-pressure, high-temperature bake is systematically utilized to drive out residual organic solvents trapped within the low-k pores, thereby restoring the material's original dielectric constant . At the 40nm node, continuous dimensional scaling makes interconnect RC delay the primary bottleneck for chip performance . The integration of highly porous carbon-doped oxide (CDO) dielectrics drastically narrows the processing window for post-etch cleans . Even minor plasma-induced densification or solvent retention can cause unacceptable shifts in wire-to-wire capacitance and induce leakage currents . Consequently, this MET5 step relies on highly optimized, low-damage hybrid or all-wet processing strategies to ensure absolute residue eradication without inducing structural collapse in the fragile nanoscale scaffolding .
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