Pre Litho Cleaning - 40nm

Consequently, aggressive acidic or highly oxidative cleans are avoided because they can deplete carbon or methyl groups from porous low-k films, leading to moisture absorption and subsequent mechanical or electrical failure .

The Pre Litho Cleaning step in the ILD5 module serves as the critical s

urface preparation phase immediately preceding Via 5 photolithography (Engineering Practice). Following the dual-layer deposition of ILD 5-1 and ILD 5-2, the wafer surface must be meticulously prepared to receive the anti-reflective coating (ARC) and photoresist layers necessary for subsequent patterning . Unlike earlier pre-litho cleaning steps in the FEOL that may interact with bare silicon or active transistor regions , this specific step operates entirely within the BEOL interconnect framework (Engineering Practice). Its primary function is to ensure a pristine dielectric surface to guarantee precise pattern transfer for Via 5, bridging the previously planarized Metal 5 layer to the subsequent routing layers . The physical and chemical mechanisms of this cleaning process revolve around the removal of adventitious organics, airborne molecular contaminants (AMCs), and trace particles without degrading the underlying dielectric (Engineering Practice). Mild wet chemical formulations, such as highly dilute Standard Clean 1 (SC1) containing ammonium hydroxide and hydrogen peroxide, are often utilized to lift particles via surface etching and electrostatic repulsion . Concurrently, the cleaning process modifies the substrate's surface free energy, which dictates the wetting behavior of the subsequent spin-coated photoresist . According to Young's equation, adjusting the polar and dispersive components of the surface free energy enhances the thermodynamic work of adhesion between the dielectric and the polymer resist . Furthermore, this step helps mitigate any surface micro-roughness anomalies that could locally alter the contact angle and induce non-uniform resist thickness . The selection of cleaning chemistry and process parameters is heavily constrained by the material properties of the ILD5 stack (Engineering Practice). Advanced BEOL integration frequently employs low-k dielectrics to minimize RC delay and capacitive coupling . Consequently, aggressive acidic or highly oxidative cleans are avoided because they can deplete carbon or methyl groups from porous low-k films, leading to moisture absorption and subsequent mechanical or electrical failure . The interaction between cleaning time, temperature, and chemical concentration is strictly optimized to balance particle removal efficiency against dielectric loss (Engineering Practice). Additionally, ensuring a clean and uniform surface is critical to maintaining the entire exposure field within the strict depth of focus (DOF) limits of the photolithography system, as underlying multi-layer topography accumulations can otherwise cause unacceptable inter-level fluctuations .

[High] Photoresist Delamination and Peeling: If the cleaning process fails to adequately raise the surface free energy or remove organic contaminants, the thermodynamic work of adhesion remains low . This leads to the photoresist lifting or peeling during the post-exposure development phase, severely degrading the lithographic pattern fidelity .
[Medium] Low-k Dielectric Damage: Excessive exposure to alkaline cleaning agents or energetic plasma treatments can strip carbon-containing functional groups from the BEOL low-k ILD . This degradation locally increases the dielectric constant, exacerbating interconnect RC delay, and may cause film delamination during subsequent thermal cycles .
[Medium] Lithographic Defect Generation via Particle Masking: Incomplete removal of particulate matter during the wet clean acts as an opaque physical mask during the photolithography exposure process (Engineering Practice). This localized blocking of incident radiation prevents the intended chemical changes in the photoresist, resulting in un-etched residues or structural shorts in the final semiconductor device .

The Pre Litho Cleaning step in the ILD5 module serves as the critical s

[High] Photoresist Delamination and Peeling: If the cleaning process fails to adequately raise the surface free energy or remove organic contaminants, the thermodynamic work of adhesion remains low . This leads to the photoresist lifting or peeling during the post-exposure development phase, severely degrading the lithographic pattern fidelity .
[Medium] Low-k Dielectric Damage: Excessive exposure to alkaline cleaning agents or energetic plasma treatments can strip carbon-containing functional groups from the BEOL low-k ILD . This degradation locally increases the dielectric constant, exacerbating interconnect RC delay, and may cause film delamination during subsequent thermal cycles .
[Medium] Lithographic Defect Generation via Particle Masking: Incomplete removal of particulate matter during the wet clean acts as an opaque physical mask during the photolithography exposure process (Engineering Practice). This localized blocking of incident radiation prevents the intended chemical changes in the photoresist, resulting in un-etched residues or structural shorts in the final semiconductor device .

40nm BSI CMOS Image SensorPreview

Process Cross-Section

Step highlight

In depth

Risks & Challenges

40nm BSI CMOS Image SensorPreview

Process Cross-Section

Step highlight

In depth

Risks & Challenges