it must selectively stop on the underlying etch stop layer (such as SiCN) to establish a proper self-aligned interface with the underlying vias .
In depth
This step forms the Metal 5 trench in the inter-layer dielectric (ILD) as part of a copper dual-damascene integration scheme . Following the Metal
5 photolithography, this fluorocarbon-based plasma etch transfers the trench pattern into the oxide or low-k dielectric . Unlike front-end pad oxide etches that primarily clear thin conformal layers over silicon, this BEOL step must precisely define high-aspect-ratio interconnect trenches to ensure reliable subsequent Ta-based liner and Cu seed deposition . Furthermore, it must selectively stop on the underlying etch stop layer (such as SiCN) to establish a proper self-aligned interface with the underlying vias .
The process relies on reactive ion etching (RIE) utilizing fluorocarbon-based plasmas . The fundamental mechanism couples physical ion bombardment with chemical reactivity . Energetic ions accelerated across the plasma sheath break structural bonds in the dielectric, while neutral fluorine and CFx radicals react with the surface to form volatile byproducts like SiF4 and COx . This process is governed by Langmuir–Hinshelwood surface kinetics, where the etch rate depends heavily on radical adsorption coverage and ion-assisted product desorption . Concurrently, carbon-rich radicals form a fluorocarbon polymer layer on the trench sidewalls, preventing lateral chemical attack and driving the highly anisotropic profile necessary for dense BEOL interconnects .
The choice of fluorocarbon chemistry is dictated by the need for high etch selectivity between the silicon-oxygen-carbon based ILD and the silicon-carbon-nitride (SiCN) etch stop layer . By adjusting the fluorine-to-carbon (F:C) ratio in the plasma, engineers can precisely tune the balance between protective polymer deposition and active chemical etching . A lower F:C ratio enhances polymer formation on all surfaces, which increases the selectivity to the underlying SiCN layer but requires higher ion energies to physically punch through the polymer at the trench bottom to sustain the downward etch . Operating at optimized substrate temperatures further regulates the volatility of reaction byproducts, preventing excessive sidewall deposition that could otherwise lead to severe profile distortion .
At the 40nm technology node, stringent constraints on interconnect RC delay necessitate the use of low-k or porous SiOCH dielectrics . These low-k materials have significantly weaker mechanical strength and higher susceptibility to plasma damage than standard SiO2 . Scaling device dimensions to this regime intensifies the fundamental physical trade-off between switching speed and parasitic capacitance . Therefore, the ILD 4-2 etch must minimize plasma-induced damage that strips carbon from the low-k film, which would otherwise locally increase the dielectric constant . The strict critical dimension control required for nanoscale multi-level interconnect reliability makes managing localized etch loading effects strictly critical for preventing systematic pattern collapse .
Risks & Challenges
[High] Trench Profile Distortion and Wiggling: In narrow trenches, excessive lateral etching or unbalanced passivation can cause bowing, while compressive residual stress from masking layers can induce structural wiggling in mechanically weak porous dielectrics .
[High] Etch Stop Layer (ESL) Punch-Through: If the plasma F:C ratio is too high, the process loses chemical selectivity and rapidly consumes the underlying SiCN etch stop layer . This can expose underlying metal to the plasma, causing conductive material to sputter onto the dielectric sidewalls and resulting in severe electrical shorts .
[Medium] Incomplete Trench Etch (Etch Stop): High-aspect-ratio dual-damascene structures restrict radical and ion transport to the trench bottom . If the fluorocarbon polymer deposition rate outpaces the ion-assisted sputtering rate, the etch process prematurely arrests, leaving residual dielectric that causes open circuits .
[Medium] Plasma-Induced Damage (PID) to Low-k: Exposure of porous SiOCH dielectrics to energetic plasmas strips methyl groups from the matrix . This chemically alters the sidewalls into a hydrophilic, higher-k SiO2-like state, worsening parasitic capacitance and fundamentally degrading the switching speed limits of the device .