40nm BSI CMOS Image SensorPreview

rough prior to via metallization [P1]. Following the bulk ILD 5-2 oxide etch, the underlying SiCN layer acts as a barrier that prevents the oxide etch chemistry from inadvertently attacking the underlying Metal 5 copper interconnects [A1]. By selectively removing this SiCN layer at the bottom of the Via 5 structures, the process exposes the copper surface to establish electrical continuity for the subsequent Metal 6 trench formation and fill [A1]. This step is distinct from earlier SiCN etches (such as ILD 1-1 or 2-1) because Via 5 typically handles power routing or larger global signal distributions rather than dense local routing, often necessitating slightly larger critical dimensions and unique pattern density considerations [A1]. Furthermore, this step prepares the wafer for ashing and subsequent Metal 6 lithography, ensuring that the via bottom is clean and fully opened without degrading the surrounding inter-layer dielectric (ILD) [P3]. The SiCN etch relies on a fluorinated plasma chemistry, where fluorine atoms and CFx radicals react with the Si-C-N network to form volatile byproducts such as SiF4, COx, and NOx [P1]. The process is driven by the competition between chemical etching and ion-assisted physical bombardment, which breaks surface bonds and promotes the desorption of reaction products [P1]. Because the overlying SiO2-based ILD 5-2 is already patterned, the etch chemistry must be highly selective to avoid expanding the via critical dimension or eroding the oxide sidewalls [A1]. To achieve this, gas mixtures containing fluorocarbons are utilized, often operating in a polymerizing regime where carbon-rich radicals form a protective fluorocarbon polymer layer on the oxide sidewalls [P1]. Physical ion bombardment selectively clears this polymer from the horizontal via bottom, allowing the fluorine radicals to continuously react with the exposed SiCN film [P1]. SiCN is specifically chosen as the etch-stop and diffusion barrier layer because it provides superior etch selectivity relative to low-k SiO2 or a-SiOC:H dielectrics under fluorinated plasma exposure [P1]. The precise composition of the SiCN layer—specifically its carbon and hydrogen content—determines its network density and surface reaction pathways [P1]. For instance, carbon incorporated into the Si-N network backbone increases film density and suppresses etching, whereas terminal carbon groups are more readily fluorinated and accelerate the etch rate [P1]. During the etch process, tuning the carbon-to-fluorine (C/F) ratio in the plasma strongly modulates the polymer deposition rate, which in turn dictates the etch selectivity between the SiCN layer and the surrounding dielectrics [P2]. In advanced integration schemes, maintaining strict control over this selectivity is paramount to prevent via-to-line misalignment or over-etching, which can degrade time-dependent dielectric breakdown (TDDB) reliability [A2]. At the 40nm node, the high aspect ratios and dense pattern layouts of the BEOL stack make the integration extremely sensitive to mechanical instability and etch non-uniformity [P3]. Any failure to uniformly open the SiCN layer across the wafer can result in systematic interconnect defects, such as electrical opens or abnormally high via contact resistance [P3]. Variations in the preceding lithography step, caused by factors like optical proximity effects, can lead to local differences in via sizes [T2]. Consequently, the SiCN etch process window must be wide enough to clear the smallest vias without over-etching and damaging the copper barrier in the larger, more isolated vias [A1]. This requires an integrated process optimization approach rather than isolated parameter tuning, ensuring that the defect density is minimized while achieving low-resistance vertical interconnects [P3].