What is the 14nm FinFET semiconductor process flow?

The 14nm FinFET process flow is an advanced semiconductor manufacturing sequence that uses three-dimensional fin-shaped transistor structures instead of planar transistors. The fins provide better electrostatic control of the channel, significantly reducing short-channel effects and leakage current while enabling continued scaling beyond the limits of planar technology.

How does 14nm FinFET differ from 28nm planar technology?

The primary difference is the transistor architecture: 14nm uses 3D fin structures where the gate wraps around the channel on three sides, while 28nm uses traditional planar (flat) transistors. This tri-gate structure provides superior electrostatic control, enabling ~50% power reduction or ~20% performance improvement at the same power. The process flow also introduces new modules like fin patterning (SADP/SAQP), fin recess, and epitaxial source/drain wrapping around fins.

How many process steps are in the 14nm FinFET flow?

The 14nm FinFET process flow on SemiFlows contains 362 detailed process steps, spanning fin formation, gate patterning, source/drain engineering, contact metallization, and back-end-of-line interconnects.

What is SADP in 14nm FinFET manufacturing?

SADP (Self-Aligned Double Patterning) is a lithography technique used in 14nm FinFET manufacturing to create fin patterns at pitches below the resolution limit of single-exposure lithography. It involves depositing a conformal spacer film on mandrel structures, then removing the mandrels to leave spacer pairs that define the fin locations at half the mandrel pitch.

14nm FinFET - 14nm Process Flow

14nm FinFET Process Flow: Comprehensive Technical Overview

Introduction

The 14nm FinFET process represents a landmark inflection point in semiconductor manufacturing, marking the broad industry transition from planar bulk CMOS to three-dimensional transistor architectures. At this node, classical scaling of gate length and oxide thickness alone could no longer deliver acceptable electrostatic control over the channel, driving the adoption of the fin-shaped field-effect transistor (FinFET) as the dominant device architecture.

In a FinFET, the channel is formed in a narrow, vertically-oriented silicon fin that protrudes above the substrate. The gate electrode wraps around three sides of this fin — top and both sidewalls — creating a tri-gate or quasi-planar electrostatic environment that dramatically improves gate control over the channel potential. This geometry suppresses short-channel effects such as drain-induced barrier lowering (DIBL) and subthreshold slope degradation that plagued planar devices at equivalent gate lengths. The 14nm node typically achieves fin widths well below the lithographic resolution limit through sidewall image transfer (SIT) patterning, and integrates a high-κ metal gate (HKMG) stack in a replacement metal gate (RMG) flow. The resulting process involves approximately 362 discrete fabrication steps organized into tightly coupled modules spanning the full FEOL–MOL–BEOL stack.

Front-End-of-Line (FEOL)

The FEOL encompasses all steps from substrate preparation through transistor formation, and at the 14nm node this is dominated by fin patterning, isolation engineering, and gate stack integration.

Fin Definition and Isolation

14nm FinFET Process Flow: Comprehensive Technical Overview

Introduction

Front-End-of-Line (FEOL)

The FEOL encompasses all steps from substrate preparation through transistor formation, and at the 14nm node this is dominated by fin patterning, isolation engineering, and gate stack integration.

14nm FinFETPreview

14nm FinFET

Enter the flow from its first step

Process Overview

14nm FinFET Process Flow: Comprehensive Technical Overview

Introduction

Front-End-of-Line (FEOL)

Fin Definition and Isolation

Key integration ideas

Module Distribution

Step index

14nm FinFETPreview

14nm FinFET

Enter the flow from its first step

Process Overview

14nm FinFET Process Flow: Comprehensive Technical Overview

Introduction

Front-End-of-Line (FEOL)

Fin Definition and Isolation

Key integration ideas

Module Distribution

Step index