40nm BSI CMOS Image SensorPreview

e the Floating Diffusion (FD) regions in a CMOS image sensor prior to N-type ion implantation [P3]. Positioned immediately after the general NMOS source/drain and primary FD implants, this specific photo step defines a localized implant window—often between shared transfer gates (T1 and T2)—to tailor the final FD doping profile [P1]. The primary objective is to create a patterned photoresist barrier that strictly blocks incoming ions from entering the pinned photodiode and other sensitive pixel regions, while allowing dopants only into the designated FD area [T1]. By precisely defining this boundary, the step sets up the subsequent implantation to achieve the required charge-voltage conversion node without degrading the carefully engineered potential pinning of the adjacent photodiode [P2]. The lithographic process relies on the photochemical transformation of a photoresist layer upon exposure to deep ultraviolet light, followed by selective development to open the implant windows [T1]. The resolution of these windows is fundamentally governed by the Rayleigh diffraction formula, which dictates the physical limits of feature size control based on wavelength and numerical aperture [T1]. Once the resist is patterned, its thickness and stopping power must be sufficient to absorb the kinetic energy of the subsequent dopant ions, preventing them from following their normal Gaussian spatial distribution into protected silicon regions [T1]. The exact placement of the resist edge dictates the lateral straggle of the ensuing implant, which directly modulates the doped overlap region between the FD and the Transfer Gate (TG) [P1]. If this edge is improperly defined, the resulting overlap can induce localized high-intensity electric fields under specific bias conditions, significantly lowering the barrier for trap-assisted carrier generation and causing random telegraph signal (RTS) noise [P1]. The selection of photoresist and associated anti-reflective coatings is driven by the need to minimize critical dimension (CD) variations and optical proximity effects during exposure [T2]. The lithography parameters—such as focus, dose, and overlay—must be tightly controlled because the size and position of the opened FD window directly determine the p-n junction area and the gate overlap capacitance [P3]. Since the conversion gain of the image sensor is inversely proportional to the total floating diffusion capacitance, minimizing unnecessary lateral extension of the FD region is essential for achieving high photon-countable sensitivity [P3]. Therefore, the photoresist must be precisely aligned to the transfer gate edges; any misalignment will alter the junction capacitance and induce asymmetric electric fields that exacerbate leakage current non-uniformity across the pixel array [P1]. In a 40nm BSI (Back-Side Illuminated) architecture, pixel pitch scaling drastically increases the sensitivity of local electric fields to minor structural variations [P1]. Advanced immersion lithography is typically employed to meet the stringent overlay and resolution requirements at this nanometer scale [T1]. The thermodynamic constraints of scaling dictate that subthreshold leakage and field-enhanced generation become dominant noise sources if the FD-to-TG spacing is not perfectly controlled [T2]. Consequently, this photo step cannot merely provide basic masking; it must employ sophisticated optical proximity correction (OPC) to ensure the patterned window perfectly matches the simulated geometry, thereby suppressing electric-field-induced leakage in ultra-small pixel structures [T2].