The ashing and strip/clean step removes the heavily crosslinked, carbon-rich photoresist crust formed by ion bombardment to prevent damage to the implanted junctions and adjacent dielectrics .
Following the high-dose NMOS Source/Drain (S/D) and Floating Diffusion (FD) Ion Implantation, the wafer
is covered by a photoresist mask that has absorbed a massive dose of energetic n-type dopants . This specific ashing and strip/clean step is distinctly required to remove this High-Dose Ion-Implanted Photoresist (HDI-PR) before proceeding to the subsequent N FD tuning implants . Unlike standard lithography rework or post-etch ashing, the photoresist here has been fundamentally altered by the ion bombardment, which breaks C-H and C-C bonds to form a heavily crosslinked, carbon-rich crust . Complete removal of this crust is critical because any remaining organic or metallic residues on the FD node will act as deep-level traps, generating localized dark current and severe pixel blemishes . Furthermore, the pristine surface preparation ensures that the subsequent low-dose N FD implantation can be precisely controlled without shadowing effects from residual polymers . The physical mechanism of removal relies on a combination of radical-driven oxidation and chemically enhanced wet stripping to break down the resilient polymer chains . Conventional oxygen plasma can induce thermal degradation and ion-bombardment damage to the sensitive FD silicon lattice (Engineering Practice). Instead, advanced low-temperature processes, such as microwave-excited water vapor plasma, generate active radicals like OH, atomic O, and H at reduced pressures . These radicals react with the carbonized PR crust, converting the organic material into volatile byproducts such as CO through partial oxidation . To further address the hardened HDI-PR without inflicting physical damage, the subsequent wet stripping phase often utilizes plasma liquid-vapor activation (PLVA) or UV irradiation [P2, P4]. These activation methods introduce high-energy active species or photons that induce photochemical chain scission in the polymer backbone, drastically altering the mechanical hardness and elastic modulus of the resist surface to allow deeper solvent penetration [P2, P4]. The selection of these specific low-damage ashing and activated wet-cleaning methods is driven by the strict requirement to maintain the integrity of the implanted junctions and adjacent dielectrics . Water cooling of the wafer during plasma exposure is deliberately utilized to suppress thermal diffusion of the shallow S/D implants, which would otherwise alter the projected range and lateral straggle of the dopants [P1, T1]. Process parameters such as plasma activation voltage and UV dose dictate the concentration of active species and the extent of polymer modification; insufficient energy results in incomplete crust removal, whereas excessive energy can cause secondary crosslinking or unwanted side reactions [P2, P4]. By carefully modulating the radical flux density and solvent reactivity, the process maximizes the PR etch rate while maintaining near-infinite selectivity to the underlying silicon substrate and gate oxides [P1, P2]. At the 40nm technology node, this step requires exceptional precision because the junction depths are exceedingly shallow and the floating diffusion capacitance must be minimized to maintain high conversion gain . Any physical consumption of the silicon during the clean, or oxide loss in the isolation regions, will directly alter the effective coupling area and equivalent oxide thickness, exacerbating short-channel effects and parasitic capacitance [P3, A3]. Therefore, the synergistic combination of radical-dominant dry ashing and modified wet stripping is essential to ensure a perfectly clean, damage-free crystalline surface that supports the rigorous leakage current requirements of advanced BSI CMOS image sensors .
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