Ion implantation is selected over thermal diffusion because it provides independent control over dose and depth, enabling the formation of precise, shallow junctions at low temperatures .
This process step introduces n-type dopants to form the shared Floating Diffusion (FD) node located between a
djacent Transfer Gates (T1 and T2) in a shared-pixel architecture . In a CMOS image sensor, the FD acts as the primary charge-to-voltage conversion node, receiving photoelectrons transferred from the pinned photodiodes . Performing a dedicated FD implant separately from the standard logic NMOS Source/Drain (S/D) implant allows for independent optimization of the FD doping profile . This decoupling is essential because standard logic S/D implants target low sheet resistance via heavy doping, which would unacceptably increase the p-n junction capacitance and severely degrade the pixel's conversion gain . By precisely defining the FD in this intermediate step, the process ensures that the specific noise and capacitance requirements of the imaging array are met before proceeding to the photodiode surface passivation (P-pinning) steps . The physical operation of this step relies on ion implantation to accelerate charged n-type dopant ions into the crystalline silicon lattice . The spatial distribution of these dopants approximates a Gaussian profile governed by the implant energy, which dictates the projected range, and the dose, which sets the peak concentration . Upon entering the substrate, the introduced impurities create shallow donor levels near the conduction band, locally modulating the Fermi level to form an n-type region within the surrounding p-well . The resulting reverse-biased p-n junction acts as a capacitive storage element where the voltage swing generated per electron is inversely proportional to the total node capacitance ($C_{FD}$) . To achieve photon-countable sensitivity and minimize read noise, the implant parameters must be strictly controlled to minimize the junction depth and the depletion boundary area, thereby shrinking the p-n junction capacitance component of $C_{FD}$ . Ion implantation is selected over thermal diffusion because it provides independent control over dose and depth, enabling the formation of precise, shallow junctions at low temperatures . A tailored n-type dopant strategy is utilized for the FD to strike a balance between achieving a graded junction—which reduces peak electric fields and junction leakage—and maintaining sufficient conductivity for signal readout . The implant angle must be carefully engineered: a zero-degree tilt poses severe channeling risks that can deepen the junction unexpectedly , while an optimized tilt and twist angle prevents channeling and limits the lateral straggle under the transfer gates (T1 and T2) . Limiting this lateral diffusion is highly critical, as excessive spatial overlap between the FD diffusion and the transfer gate significantly increases gate overlap capacitance, which has been identified as a dominant detractor to conversion gain . At the 40nm process node, pixel dimensions and transistor channel lengths are highly constrained, making 3D edge capacitance and fringing electric fields dominant factors in FD node design . The physical spacing between T1 and T2 is exceptionally narrow, requiring highly conformal photoresist definition and precise beam current control to avoid dose rate effects and beam-induced substrate charging . Furthermore, managing implant-induced crystalline damage is paramount; unannealed point defects act as generation-recombination centers that manifest as white pixel blemishes and elevated dark current . Thus, the FD implant energy and dose must be carefully balanced with the subsequent thermal budget to ensure adequate dopant activation while preventing excessive transient enhanced diffusion that would broaden the FD profile and ruin the charge conversion efficiency .
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