Following the formation of the sidewall spacers (SWS) and subsequent cleaning, the NMOS Source/Drain (S/D) and Floating Diffusion (FD) Ion Implantation (IIP) step establishes the heavily doped N+ regions T1.This process step is fundamentally required to provide low-resistance contact regions for NMOS logic transistors and to form the charge-to-voltage conversion node—the floating diffusion—within the pixel architecture P3.Performing this high-dose implantation after the spacer formation ensures