the thermal energy drives the outgassing of incorporated hydrogen and moisture, promoting the cross-linking of Si-O-Si bonds and causing volumetric shrinkage of the dielectric material .
In depth
The STI Final Densification Anneal follows the chemical-mechanical planarization (CMP) and post-CMP cleaning s
teps, serving as a critical thermal treatment before the removal of the protective silicon nitride (SiN) pad . At this stage in the 40nm BSI CMOS Image Sensor flow, the shallow trenches are filled and planarized, but the deposited oxide retains non-ideal structural characteristics and residual mechanical stress . This final anneal is required to fully densify the remaining isolation oxide, modifying its molecular structure to approach the density of thermally grown oxide . By performing this step before the Wet Deglaze Etch and SiN Strip, the process ensures that the STI oxide exhibits a low and highly predictable wet etch rate, which is essential for precise control of the final STI step height and planarity . The core physical mechanism of this densification anneal involves the structural rearrangement of the silicon dioxide network and visco-elastic stress relaxation at elevated temperatures . During deposition, chemical vapor deposition (CVD) oxides incorporate moisture and exhibit microscopic porosity, leading to intrinsic film stress and lower physical density . When subjected to high-temperature annealing, typically above 800°C, the oxide enters a viscous flow regime where the elastic stresses relax . Concurrently, the thermal energy drives the outgassing of incorporated hydrogen and moisture, promoting the cross-linking of Si-O-Si bonds and causing volumetric shrinkage of the dielectric material . Because the oxide is constrained by the rigid silicon trench walls, this volumetric contraction initially generates significant thermo-mechanical stress . However, operating in the visco-elastic regime allows the material to plastically deform and redistribute these forces, ultimately minimizing localized stress concentrations at the trench corners . The selection of the anneal temperature, ambient gas, and duration is governed by a strict trade-off between effective densification and the suppression of stress-induced silicon defects . Higher temperatures exponentially increase the visco-elastic flow rate of the oxide, facilitating more complete stress relaxation and densification . However, excessive thermal budgets can cause the densified oxide to exert severe compressive forces on the active silicon regions upon cooling, driven by the mismatch in thermal expansion coefficients between the silicon substrate and the oxide trench fill . This stress can propagate dislocations along the <111> slip planes in the silicon substrate, providing pathways for stress-induced leakage current (SILC) that severely degrades device performance . Therefore, the heating and cooling ramp rates must be carefully tuned to prevent thermal shock and dynamically manage the final residual stress state . In a 40nm BSI CMOS Image Sensor technology, meticulous management of STI-induced stress is particularly critical because mechanical stress directly modulates the semiconductor band structure and carrier mobility . Furthermore, stress-induced crystal defects in the active region act as generation-recombination centers, which are the primary source of white pixel defects and dark current in image sensors . Unlike standard logic processes that deliberately utilize highly stressed STI for channel strain engineering to boost mobility , image sensor flows prioritize absolute defect minimization and leakage suppression . Performing this densification after CMP reduces the total volume of oxide that undergoes high-temperature shrinkage compared to pre-CMP densification, thereby managing the macroscopic compressive stress applied to the narrow nanoscale active area pitches .
Risks & Challenges
[High] Stress-Induced Dislocation Formation: Volumetric shrinkage of the trench-fill oxide, combined with thermal expansion mismatch, concentrates thermo-mechanical stress at the trench corners . If the final stress exceeds the silicon yield strength during the anneal cooling phase, dislocations will nucleate and propagate along <111> crystal planes . These defects act as generation centers in the depletion region, leading to severe stress-induced leakage current (SILC) and degraded image sensor dark current .
[Medium] Anomalous Wet Etch Rate due to Under-Densification: If the anneal temperature or time is insufficient, the structural rearrangement of the CVD oxide will remain incomplete, leaving microscopic porosity and weak Si-O bonds . This under-densified oxide will exhibit an excessively high and non-uniform wet etch rate during the subsequent Wet Deglaze Etch step (Engineering Practice). This excessive oxide loss creates deep recesses at the isolation edges that enhance the local electric field and cause a parasitic double-peak Id-Vg characteristic .
[Medium] Wafer Warpage and Structural Deformation: The macroscopic stress generated by the densification of the STI oxide can induce significant mechanical bowing or warpage across the entire wafer . Because the visco-elastic relaxation of deep trench oxide is much slower than that of a blanket film, uneven stress distribution occurs between dense and isolated pattern areas during the thermal cycle . This warpage can alter the saturation current dependence on channel width due to localized stress variations .
[Low] Active Area Oxidation and Active CD Loss: If an oxidizing ambient is utilized during the high-temperature anneal, oxygen can diffuse through the planarized oxide and react with the silicon at the trench sidewalls . While minor oxidation helps round the trench corners and alleviate local stress , excessive oxidation consumes the silicon active area, reducing the effective channel width and shifting the electrical parameters of the final nanoscale transistors .