Its primary objective is to physically carve a highly controlled trench into the crystalline silicon substrate, establishing the physical boundaries that isolate adjacent active transistor regions .
In depth
The Silicon (Si) Etch step in the Shallow Trench Isolation (STI) module directly follows the patte
rning of the nitride and pad oxide hard mask . Its primary objective is to physically carve a highly controlled trench into the crystalline silicon substrate, establishing the physical boundaries that isolate adjacent active transistor regions . Unlike older LOCOS methods, STI provides nearly zero field-region lateral encroachment, which is essential for preserving active area in high-density deep-submicron integration . In the context of a nanoscale Backside Illuminated (BSI) CMOS Image Sensor, this isolation is critical not only for standard electrical isolation but also for suppressing parasitic conduction and crosstalk between adjacent pixels . The resulting trench geometry directly dictates the success of the subsequent oxide gap-fill and determines the initial mechanical stress state of the final device . The Si Etch process is driven by reactive ion etching (RIE) principles in a low-pressure discharge plasma, relying on the synergistic interaction between neutral radicals and energized ions . A typical chemistry utilizes a mixture of chlorine (Cl2) and oxygen (O2) . Halogen radicals chemically adsorb onto the exposed silicon surface to form volatile etch byproducts such as SiClx, facilitating material removal . Simultaneously, the O2 additive reacts with these byproducts to form a thin silicon oxychloride passivating film on the trench sidewalls, protecting them from lateral etching . The high-energy ions, accelerated across the plasma sheath by the electric field, provide the directional kinetic energy necessary to break surface bonds at the trench bottom and sputter away the passivating film locally, ensuring highly anisotropic pattern transfer . The necessity of a tapered trench profile dictates the precise tuning of the plasma parameters during this step . The trench sidewall angle must be maintained greater than approximately 80 degrees to ensure isolation depth while facilitating a void-free dielectric fill in later Chemical Vapor Deposition (CVD) steps . If the profile is too vertical or re-entrant, the subsequent gap-fill oxide will pinch off at the top, creating voids that compromise structural and electrical integrity . Furthermore, the etch process must engineer a rounded trench bottom . Sharp corners at the trench bottom act as stress concentrators during thermal cycling, which can induce crystalline defects and alter carrier mobility through the piezoresistance effect . Therefore, the ratio of passivant-forming gases (O2) to etchant gases (Cl2), alongside ion bombardment energy, must be carefully balanced to achieve the desired taper and bottom rounding . For nanoscale advanced nodes, the purely geometric constraints of the STI trench are intrinsically linked to thermodynamic and device physics limits . As active pitches scale down, any surface roughness generated by plasma ion bombardment on the trench sidewalls can create interface traps, which severely degrade device performance by increasing subthreshold leakage . In image sensors, such leakage directly translates to elevated dark current and white pixel defects (Engineering Practice). Consequently, the Si Etch step must be carefully controlled and is immediately followed by rigorous strip/clean, sidewall passivation, and high-temperature liner oxidation steps to repair etch-induced lattice damage and round the top corners .
Risks & Challenges
[High] Chamber Condition Drift: During Cl2/O2 etching, silicon oxychloride etch byproducts deposit onto the reactor chamber walls . These deposits modify the surface recombination probabilities of reactive species, shifting the plasma radical concentration and electron temperature over time, which degrades wafer-to-wafer etch rate and profile reproducibility .
[High] Mechanical Stress and Double-Peak Transistor Effect: If the etch recipe fails to produce a sufficiently rounded trench bottom and corners, severe mechanical stress will concentrate at these sharp geometric transitions during subsequent thermal oxidation steps . This stress alters the local silicon band structure and electric field distribution, potentially causing a parasitic parallel channel that manifests as a threshold voltage double-peak phenomenon in the transistor characteristics .
[Medium] Dielectric Gap-Fill Voids: An improper balance between the Cl2 etchant and O2 passivant can result in a sidewall angle that is perfectly vertical or slightly bowed, rather than the required >80° tapered profile . This lack of taper prevents conformal deposition during the subsequent CVD gap-fill steps, leading to premature pinch-off at the trench opening and the formation of internal voids .
[Medium] Plasma-Induced Surface Damage: Excessive ion bombardment energy, while increasing etch anisotropy, inflicts physical damage to the crystalline silicon lattice on the trench sidewalls . This damage generates dense interface traps that act as generation-recombination centers, significantly increasing subthreshold leakage currents and generating unacceptable dark current levels in CMOS image sensor arrays .