This step transfers the Via 4 (V4) pattern from the photoresist into the ILD 4-2 dielectric layer to establish vertical connectivity between Metal 4 and Metal 5 A2.Following the V4 lithography step, an anisotropic plasma etch is utilized to selectively remove the exposed oxide while preserving the underlying ILD 4-1 SiCN etch stop layer A2.Unlike shallow pad oxide etches that primarily clear superficial silicon interfaces for front-end devices, this deep back-end-of-line (BEOL) oxide etch must n