40nm BSI CMOS Image SensorPreview

, leaving the Ta-based liner exposed on the field dielectric [P1]. The Ta-based liner CMP step, often termed barrier CMP, is required to remove this remaining liner and polish the entire interconnect stack [P1]. This process electrically isolates the MET4 copper lines by clearing conductive material from the field dielectric, preventing short circuits between adjacent lines [A1]. It prepares a globally planarized surface, encompassing Cu in trenches, sidewall liners, and dielectric material, for the subsequent Post CMP Cleaning and ILD 4-1 deposition [P1]. This step is distinct from other Ta-liner CMP steps in the flow because it specifically defines the MET4 interconnect level, which in a BSI image sensor architecture demands precise topography control prior to upper-level routing or optical shielding module formations [A1]. The CMP process is jointly governed by classical tribology and electrochemical kinetics [P1]. Unlike the preceding Cu CMP step, which uses oxidants like H2O2 to chemically convert copper into easily removable CuO or Cu(OH)2 layers [P2], the Ta-based liner is chemically highly stable and resistant to chemical etching (Engineering Practice). Consequently, the removal of the Ta adhesion and diffusion barrier is often purely mechanical [P2]. The mechanical action relies on abrasive particles in the slurry shearing off the barrier material under applied polishing pad pressure and relative velocity [P2]. To prevent the relatively soft copper from being rapidly etched away while the hard Ta is ground down, the slurry chemistry must simultaneously induce a protective passivation layer on the exposed Cu surfaces [P2]. Material removal during this step can be mathematically described by Preston’s law, where the removal rate is proportional to pressure and relative velocity [P1]. Because the Ta liner removal is primarily driven by mechanical abrasion, damascene structures must often be overpolished considerably to completely clear the Ta residue across the entire sample [P2]. A high metal-to-dielectric removal selectivity is strictly required during this step to prevent excessive thinning and erosion of the inter-level dielectric during the extended overpolish phase [P2]. Furthermore, pattern density and line-width effects significantly alter local contact mechanics and mass transport, meaning that removal rates and selectivities measured on blanket wafers cannot be directly extrapolated to high-density patterned structures [P1]. Slurry pH acts as a key factor in balancing these disparate material removal rates and maintaining the colloidal stability of the abrasive particles [P4]. At the 40nm technology node, decreasing interconnect dimensions pose unique planarization challenges for integrated back-end-of-line (BEOL) unit processes [P1]. As line width and spacing shrink, the local stress distribution changes significantly, leading to a pronounced degradation in Cu-to-liner selectivity on patterned structures [P1]. While highly advanced sub-14nm nodes may replace the traditional thick TaN/Ta liner with ultra-thin cobalt encapsulation to reduce via contact resistance [A1], the 40nm node continues to rely on the Ta-based barrier to effectively prevent Cu diffusion into the surrounding dielectric [P3]. This necessitates precise optimization of the barrier CMP step to manage the critical trade-off between ensuring complete barrier clearing and minimizing the step-height variations or dishing induced by pattern dependencies [P3].