40nm BSI CMOS Image SensorPreview

e back-end-of-line (BEOL) module, specifically executed within a via-first, trench-last dual-damascene integration scheme [P2]. Following the ILD 3-2 Oxide and ILD 3-1 SiCN via etches and subsequent cleans, the wafer surface contains deep, open Via 3 (V3) cavities (Engineering Practice). The primary function of this photo step is to define the lateral interconnect routing patterns for the M4 layer in the photoresist, preparing the ILD 3-2 oxide for the subsequent trench etch [A2]. Unlike Frontside Deep Trench or Shallow Trench Isolation (STI) lithography steps which define deep structural features in the silicon substrate for active device isolation (Engineering Practice), or Metal 0 / Metal 1 steps which interface directly with highly dense transistor contacts [T2], the M4 step manages mid-tier signal and power routing. In a 40nm BSI CMOS Image Sensor architecture, these mid-tier layers must maintain strict dimensional control to balance parasitic capacitance and resistance, ensuring high-speed signal propagation from the pixel array without obstructing the backside optical path [P1]. The physical mechanism of this step relies on optical projection lithography and complex gap-fill polymer chemistry [T2]. Because the pre-existing V3 holes create severe surface topography, a sacrificial gap-fill material or bottom anti-reflective coating (BARC) is first spin-coated onto the wafer [P2]. This material serves a dual physical purpose: it planarizes the surface to provide a uniform focal plane for the photoresist, and it plugs the V3 holes to protect the underlying Metal 3 layer during the upcoming M4 trench etch [A2]. Once the photoresist is applied, optical exposure modifies the polymer's chemical solubility [T2]. The resolution of this pattern is governed by the Rayleigh criterion, where the minimum resolvable feature size depends fundamentally on the exposure wavelength and the numerical aperture (NA) of the lens system [T2]. Because dense and isolated routing lines experience different optical diffraction interference, rigorous optical proximity correction (OPC) is applied to the photomask to intentionally reshape patterns, preventing systematic variations such as line-end shortening [T3]. Material and method selections for this step are driven by the stringent demands of Cu/low-k interconnect scaling [P3]. A via-first, trench-last approach is selected because it simplifies the deep etching of high-aspect-ratio vias before the wider trenches are formed, minimizing the risk of polymer micro-masking [P2]. The dimensions defined during this lithography step directly dictate the final copper wire geometry, which governs the interconnect RC delay [P1]. As line width shrinks, electron surface scattering and grain-boundary scattering increase dramatically, elevating the effective copper resistivity [P1]. Therefore, the photoresist critical dimensions (CD) must be precisely targeted to ensure the trench is wide enough to mitigate size-effect resistivity increases, but narrow enough to prevent excessive line-to-line capacitive coupling through the low-k dielectric [P1]. The sacrificial via-fill material is specifically selected for its etch rate matching with the photoresist and its selectivity against the ILD oxide, ensuring it can be synchronously removed during the subsequent trench etch without leaving residues [A2]. At the 40nm node, the physical limitations of wavelength scaling require the use of immersion lithography and highly optimized resist chemistries to maintain an adequate depth of focus [T2]. The statistical nature of photon absorption and polymer chain scission in the resist manifests as line-edge roughness (LER) [T3]. In highly scaled Cu/low-k systems, this lithography-induced LER transfers directly into the trench sidewalls during the next etch step, subsequently amplifying electron surface scattering in the copper line and degrading overall circuit speed [P1]. Consequently, exposure dose, focus, and post-exposure bake temperatures must be tightly co-optimized to minimize resist profile degradation while ensuring complete pattern fidelity over the complex underlying topography [P2].