40nm BSI CMOS Image SensorPreview

renches and vias are subsequently filled with copper (Cu) [A1]. Following the MET4 trench etch and post-ash clean, this deposition step forms a Ta-based liner to completely surround and isolate the target Cu interconnect [A1]. Without this diffusion limiting layer, Cu atoms can easily migrate into the surrounding inter-layer dielectric (ILD), where they create deep trap states or reagglomerate to form conductive shortcuts, leading to catastrophic dielectric leakage [P3]. This specific MET4 deposition step prepares the etched trench for the subsequent Cu seed layer, providing both a physical diffusion barrier and a chemical adhesion promoter to mechanically anchor the Cu to the ILD [A2]. Compared to similar steps in lower metal layers (e.g. (Engineering Practice), MET1), the MET4 layer in a 40nm CMOS image sensor typically handles higher global routing currents, requiring specific tuning of the liner thickness to balance electromigration robustness with overall interconnect resistance (Engineering Practice). The physical mechanism of the Ta-based liner relies on thermodynamic immiscibility and dense microstructural properties [P4]. Tantalum (Ta) and tantalum nitride (TaN) are refractory metals that are inherently immiscible with Cu at standard processing temperatures, minimizing the thermodynamic driving force for bulk interdiffusion [P4]. Typically deposited as a bilayer, the TaN component acts as the primary diffusion barrier due to its amorphous-like, dense structure that lacks rapid grain-boundary diffusion paths, while the pure Ta surface layer serves as an adhesion promoter [P1]. The metallic Ta layer maintains a lower interfacial energy with Cu compared to bare dielectrics, which improves Cu wettability and significantly suppresses electromigration (EM) failures [P1]. Furthermore, encapsulating the Cu with this liner prevents the formation of brittle Cu-silicides with any underlying silicon-based structures, which would otherwise cause volumetric expansion and localized semiconductor contamination [P3]. Physical vapor deposition (PVD) is traditionally used to deposit these Ta/TaN bilayers to ensure optimal material purity and density [P2]. A Ta-based system is explicitly selected over alternative metals like titanium because Cu and Ti readily form a bulk alloy, which would severely degrade the conductivity of the interconnect [P4]. However, PVD techniques inherently suffer from poor conformality and step coverage in high-aspect-ratio trenches, making the ratio of bottom-to-sidewall thickness a critical process monitor [P1]. To optimize this coverage, the process must precisely balance the sputtering plasma power, gas pressure, and wafer bias to ensure sufficient sidewall protection without generating excessive overhang that pinches off the trench opening [A1]. At the 40nm technology node, the critical dimensions (CD) of the interconnects are drastically reduced, meaning the barrier layer occupies a continuously increasing fraction of the total conductor volume [A1]. Because Ta and TaN possess significantly higher electrical resistivity than pure Cu, this volumetric displacement reduces the cross-sectional area available for highly conductive copper, leading to increased electron scattering and a pronounced rise in total interconnect resistivity [A1]. Consequently, an increase in the resistance-capacitance (RC) delay occurs, which can elevate power consumption and limit the switching speed of the integrated circuit [A1]. Therefore, the Ta-based liner must be deposited as thin as physically possible while maintaining extremely high shielding integrity to compensate for the restricted thickness budget [P3].