40nm BSI CMOS Image SensorPreview

from other routine resist strip operations in the flow because the underlying Metal 4 copper has just been physically exposed by the removal of the SiCN barrier (Engineering Practice). The primary objective is to entirely remove the remaining photoresist, anti-reflective coatings, and complex post-etch residues (PER) generated during the deep via etch without damaging the exposed copper or the surrounding low-k dielectric [P1, P4]. A pristine, residue-free surface is strictly required to prevent lithographic defocus in the subsequent M5 trench patterning and to avert long-term reliability issues, such as time-dependent dielectric breakdown (TDDB) in scaled-down devices [P4]. The post-etch residues present at this stage are predominantly highly crosslinked fluorocarbon (CFx) polymers, which were intentionally deposited during the dielectric etch to maintain anisotropic profiles [P1], alongside sputtered copper and carbon-rich resist crusts [P3]. Conventional high-temperature oxygen plasma ashing is detrimental here; it causes the photoresist to undergo thermochemical crosslinking and harden into an intractable crust [P3], while simultaneously inducing severe damage to porous low-k dielectrics by depleting carbon (e.g., breaking Si-CH3 bonds) [P1, P2]. To mitigate these conflicting challenges, advanced removal mechanisms deploy a combination of low-damage structural modification followed by selective wet dissolution [P1]. For example, ultraviolet (UV) irradiation at specific wavelengths (such as nanoscale) is utilized to induce photochemical chain scission within the polymer backbone [P1]. This photon energy breaks C-C and C-F bonds, drastically reducing the polymer's crosslink density and increasing its surface polarity, which physically enables the subsequent wet stripping chemistry to penetrate and dissolve the network [P1]. Alternatively, low-temperature in-situ plasma ashing can be employed to volatilize organics while actively preventing the thermal hardening of the resist [P3]. The selection of the wet cleaning chemistry is strictly bounded by the simultaneous need to dissolve the modified fluorocarbon residues while passivating the newly exposed metallic copper and protecting the sensitive low-k dielectric [A3]. Highly oxidative or aggressive aqueous solutions, such as dilute HF, are fundamentally avoided because they cause unacceptable dimensional loss by isotropically etching the dielectric to lift off polymers [P1] and can rapidly corrode exposed metal structures [A3]. Instead, engineered formulations incorporating organic solvents, balanced oxidizers, and specific corrosion inhibitors (such as long-chain alkylamines) are favored, as they selectively dissolve modified residues while selectively passivating metallic surfaces through adsorption [A3]. The process parameter interaction window requires a delicate balance: the modification energy (UV dose or plasma power) must be sufficiently high to break polymer bonds, yet bounded to prevent an increase in the dielectric constant (k-value) or structural crosslinking of the low-k matrix [P1, P2]. At the 40nm node for BSI CMOS Image Sensors, the scaling of interconnect dimensions fundamentally restricts the process window for residue removal [P2]. Because strict critical dimension (CD) control is paramount at these pitches, the historical method of polymer removal via intentional dielectric under-etching is no longer viable [P2]. Furthermore, the required transition to highly porous low-k materials—necessary to minimize RC delay and suppress interfacial scattering as interconnects scale [P4]—amplifies the structure's vulnerability to plasma-induced top-corner damage [P2]. If conventional plasma is used, this damaged region is easily attacked during subsequent wet cleans, resulting in non-planar top surfaces that directly cause severe interline capacitance and isolation failures [P2]. Consequently, this highly selective, synergistic modification-and-strip approach is vital for ensuring interconnect reliability [P4].