PMD 2 - Deposition - 40nm

PMD 2 extends the dielectric volume above PMD 1 to support subsequent interconnect layers (Engineering Practice).

PMD 2 - Deposition is a critical bulk dielectric deposition step within the Middle-of-Line (MOL) module, occurring after the initial PMD 1 gap-fill and Contact Etch Stop Layers (CESL) *

(Engineering Practice)*. Its primary function is to build sufficient dielectric thickness to electrically isolate the Front-End-of-Line (FEOL) devices from the upcoming first metal interconnects (M1) . As device dimensions scale down to nanoscale, a single PMD deposition step cannot simultaneously satisfy the stringent requirements for high-aspect-ratio void-free gap filling and thick planarization bulk . Therefore, the PMD is split into multiple stages, where PMD 1 focuses on conformal filling between tight gate pitches, while PMD 2 acts as the structural bulk layer to provide the necessary thickness and mechanical support for subsequent PMD 3 deposition and chemical-mechanical planarization (CMP) steps . The deposition of PMD 2 typically employs plasma-enhanced chemical vapor deposition (PECVD) or sub-atmospheric CVD (SACVD) using tetraethoxysilane (TEOS) and oxygen/ozone precursors . In an SACVD process, ozone acts as a strong oxidant that reacts with TEOS on the heated wafer surface, producing a highly mobile intermediate species that flows into remaining topological depressions before fully oxidizing into solid silicon dioxide (SiO2) . This reaction pathway ensures excellent step coverage and helps eliminate any residual seams left by the PMD 1 layer (Engineering Practice). Alternatively, PECVD utilizes a plasma to dissociate precursor gases, depositing a denser but less conformal film, which is suitable for building vertical thickness rapidly once the critical gaps are already filled . The resulting oxide thickness directly determines the vertical distance between the gate and the eventual metal interconnects, physically modulating the parasitic gate-to-contact capacitance that limits the switching speed of the MOSFET . The selection of TEOS-based oxide for PMD 2 is driven by its structural robustness and dielectric integrity, which are required to prevent dielectric breakdown under operating voltages . Dielectric breakdown becomes a significant risk if the effective oxide thickness or structural density is compromised, necessitating strict control over the deposition conditions . Key control parameters include deposition temperature, precursor flow rates, and chamber pressure, which interact to dictate the film's deposition rate, density, and intrinsic mechanical stress . Managing stress is particularly critical in multi-layer depositions; excessive tensile or compressive stress can cause wafer bowing or delamination from the underlying CESL . Consequently, deposition processes are often optimized with specific thermal budgets to balance film densification against the risk of degrading the delicate stress characteristics of the underlying strained silicon CESL layers . In a 40nm CMOS Image Sensor (CIS) architecture, minimizing electrical crosstalk requires highly precise control over the MOL dielectric uniformity . The structural integrity of the PMD 2 layer ensures that subsequent high-aspect-ratio contact etching achieves uniform landing on the source/drain regions without blowing out the sidewalls . Furthermore, utilizing multiple dielectric deposition steps helps manage the overall thermal budget, which is strictly limited to prevent dopant diffusion in shallow junctions and maintain the precise carrier concentration profiles established in the FEOL .

[High] Void Formation / Seam Opening: Even though PMD 2 is a bulk deposition, poor process tuning or insufficient mobility of precursor species can cause keyhole voids if the underlying PMD 1 topology was incompletely filled (Engineering Practice). If these internal voids are later exposed during CMP or contact etching, they will trap conductive metals during tungsten plug formation, leading to catastrophic short circuits .
[Medium] Dielectric Breakdown (TDDB): Inadequate film density or the incorporation of impurities during the bulk oxide deposition reduces the intrinsic dielectric strength of the layer . Under continuous high electric fields during device operation, this accelerates trap generation and leads to time-dependent dielectric breakdown between adjacent contacts or between a contact and the gate .
[Medium] Mechanical Stress-Induced Wafer Bowing: Thick dielectric depositions inherently accumulate internal mechanical stress . If the intrinsic stress of the PMD 2 layer is not properly balanced with the substrate and the previously deposited CESL layers, it can cause severe wafer warpage, leading to overlay errors in subsequent critical lithography steps (Engineering Practice).
[Low] Thermal Budget Exceedance: If the PMD 2 deposition requires prolonged elevated temperatures to achieve the desired film density, the accumulated thermal budget can cause undesirable thermal diffusion of dopants in the underlying shallow source/drain junctions . This unintended diffusion alters the effective channel length and subthreshold leakage current of the MOSFETs, ultimately degrading device switching performance .

PMD 2 extends the dielectric volume above PMD 1 to support subsequent interconnect layers (Engineering Practice).

PMD 2 - Deposition is a critical bulk dielectric deposition step within the Middle-of-Line (MOL) module, occurring after the initial PMD 1 gap-fill and Contact Etch Stop Layers (CESL) *

[High] Void Formation / Seam Opening: Even though PMD 2 is a bulk deposition, poor process tuning or insufficient mobility of precursor species can cause keyhole voids if the underlying PMD 1 topology was incompletely filled (Engineering Practice). If these internal voids are later exposed during CMP or contact etching, they will trap conductive metals during tungsten plug formation, leading to catastrophic short circuits .
[Medium] Dielectric Breakdown (TDDB): Inadequate film density or the incorporation of impurities during the bulk oxide deposition reduces the intrinsic dielectric strength of the layer . Under continuous high electric fields during device operation, this accelerates trap generation and leads to time-dependent dielectric breakdown between adjacent contacts or between a contact and the gate .
[Medium] Mechanical Stress-Induced Wafer Bowing: Thick dielectric depositions inherently accumulate internal mechanical stress . If the intrinsic stress of the PMD 2 layer is not properly balanced with the substrate and the previously deposited CESL layers, it can cause severe wafer warpage, leading to overlay errors in subsequent critical lithography steps (Engineering Practice).
[Low] Thermal Budget Exceedance: If the PMD 2 deposition requires prolonged elevated temperatures to achieve the desired film density, the accumulated thermal budget can cause undesirable thermal diffusion of dopants in the underlying shallow source/drain junctions . This unintended diffusion alters the effective channel length and subthreshold leakage current of the MOSFETs, ultimately degrading device switching performance .

40nm BSI CMOS Image SensorPreview

Process Cross-Section

Step highlight

In depth

Risks & Challenges

40nm BSI CMOS Image SensorPreview

Process Cross-Section

Step highlight

In depth

Risks & Challenges