40nm BSI CMOS Image SensorPreview

Etch Stop Layer (CESL) [A1]. The CESL serves a dual purpose: it acts as a highly selective barrier to protect underlying active areas during the aggressive contact hole etch, and it introduces mechanical strain into the transistor channel to enhance carrier mobility [P1]. In the context of a 40nm CMOS image sensor flow, CESL 1 is typically deposited to cover a specific device type, such as NMOS, while the subsequent CESL 2 step will provide the complementary stress type for PMOS devices [P1]. This sequential deposition and patterning form the basis of the dual-stress liner integration scheme, creating a tailored mechanical stress environment across the die [T2]. The deposition process relies on plasma-enhanced chemical vapor deposition (PECVD) to form an amorphous hydrogenated silicon nitride (a-SiNxHy) film [P1]. During deposition and subsequent curing, a stable intrinsic stress is built into the film, which is transferred to the underlying silicon substrate through the gate geometry and interface adhesion [P1]. This mechanical coupling causes a lattice distortion in the silicon channel, which breaks valley degeneracy and reduces carrier effective mass, fundamentally altering the band structure dictated by the material's periodic potential [T1]. By intentionally modifying the band structure, the device achieves a higher drive current without indefinitely lowering the threshold voltage, thereby balancing the thermodynamic limits of subthreshold leakage [T2]. PECVD is selected over conventional low-pressure chemical vapor deposition (LPCVD) because LPCVD requires temperatures exceeding 700°C, which would destroy the activated dopant profiles and exceed the thermal budget of advanced ultra-large-scale integration [P3]. Plasma enhancement introduces non-thermal energy through reactive radicals, enabling precursor decomposition and film growth at much lower substrate temperatures [P2]. The magnitude and sign of the intrinsic stress can be finely tuned from tensile to compressive by adjusting process parameters such as the ratio of low-frequency to high-frequency RF power [P4]. Low-frequency plasma increases ion bombardment, which densifies the film and introduces compressive stress, while high-frequency plasma operates in a more chemistry-controlled regime to produce tensile stress [P4]. At the 40nm technology node, performance enhancements from purely geometric scaling have reached physical limitations, making process-induced strain critical for maintaining device speed [T2]. The CESL 1 deposition specifically tailors this mechanical stress effect for one transistor type, differentiating its target intrinsic stress from the oppositely stressed CESL 2 [P1]. Additionally, the deposited silicon nitride must exhibit high density and excellent conformality to serve as an ultrathin hard mask during contact formation [A2]. If properly engineered, this conformal layer prevents the erosion of adjacent gate caps and sidewall spacers when highly selective etches are used to create complex contact hole profiles [A1].