40nm BSI CMOS Image SensorPreview

the sequential deposition of PMD layers, the wafer surface exhibits substantial layout-dependent topography that must be eliminated before contact formation [P3]. The primary objective of this step is to create an optically flat surface to satisfy the stringent Depth of Focus requirements of the subsequent Metal 0 and Contact photo step [P1]. Without adequate planarization, variations in the interlevel dielectric thickness would cause photo misalignment and destructive interference during lithography [P1]. Furthermore, achieving a uniform PMD thickness ensures consistent contact etch depths, which directly controls the contact series resistance and the ultimate drain-source current of the MOSFET [T1]. Material removal during PMD oxide CMP relies on a synergistic chemo-mechanical mechanism operating under boundary or mixed lubrication regimes at the pad-wafer interface [P2]. The chemical component generally follows a Langmuir-Hinshelwood kinetic framework, where slurry chemicals induce surface hydroxylation to soften the silicon dioxide [P1]. Subsequently, mechanical abrasion by nanoscale slurry particles removes this hydrated silicate reaction layer [P1]. The fundamental mechanical removal rate is well-described by Preston's equation, where the removal rate is proportional to the applied down pressure and relative sliding velocity [A1]. At the microscopic level, material removal is driven by high-frequency stick-slip vibrational events, where the directivity of shear force variations strongly correlates with polishing efficiency [P2]. Slurry chemistry and pad properties are carefully selected to balance planarization efficiency with defectivity control [P4]. Colloidal silica or ceria-based slurries are typically chosen because they provide optimal chemical reactivity and mechanical hardness for oxide planarization [P4]. To mitigate layout-dependent planarization differences, where sparse pattern regions experience different local pressures compared to dense regions, metal-fill dummy structures are often co-optimized with the CMP process [P3]. During the polish, real-time in-situ optical monitoring is employed to track film thickness using thin-film reflection interference models [A2]. This spectral measurement technique isolates the equivalent source spectrum of the multi-layer dielectric to precisely halt the process at the target thickness, preventing severe PMD recess or erosion [A2]. At the 40nm node, the margin for dishing and erosion is minimal due to the scaled dimensions of the device structures [P3]. The abrasive particles in the slurry possess surface charges defined by their isoelectric points, which can lead to electrostatic adhesion of residual particles on the planarized dielectric [P4]. Consequently, controlling the slurry pH is essential to optimize the electrostatic repulsion between the abrasives and the wafer surface for the upcoming Post CMP Cleaning step [P4]. Any remaining contaminants or severe thickness variations can degrade the dielectric reliability, eventually leading to catastrophic breakdown under electric field stress in the final integrated circuit [T2].