CESL 2 - Deposition - 40nm

CESL 2 deposition forms a silicon nitride or silicon carbonitride layer that prevents over-etching during contact via generation .

Following dopant activation and the initial CESL 1 deposition, the CESL 2 deposition completes the Contact Etch Stop Layer stack before the thick Pre-Metal Dielectric

(PMD) deposition . In a 40nm CMOS image sensor flow, integrating a secondary CESL layer serves two primary functions: providing highly selective etch-stop capabilities during the subsequent high-aspect-ratio contact hole formation, and modulating intrinsic channel stress [A1, P4]. Unlike CESL 1, which typically acts as a direct, thin protective liner over the gate and source/drain regions to prevent plasma damage, CESL 2 is specifically engineered to dictate the structural and mechanical properties of the MOL architecture (Engineering Practice). This multi-layer etch-stop scheme enhances the interconnect alignment margin and prevents over-etching into the active silicon during contact via generation, a physical mechanism fundamental to yielding reliable self-aligned contact structures . The deposition of the silicon nitride or carbon-doped nitride CESL 2 film relies on Plasma-Enhanced Atomic Layer Deposition (PEALD) or advanced PECVD to meet the strict thermal budget requirements of modern ULSI technology . The essence of the PEALD process involves alternating, surface-self-limiting chemisorption of a silicon precursor and nitrogen radicals generated by an RF plasma . The non-equilibrium plasma provides high-energy reactive species that lower the activation energy required for nitridation, enabling the formation of a dense Si-N network at temperatures significantly lower than those required for traditional thermal LPCVD . Simultaneously, directional ion bombardment during the plasma half-cycle physically densifies the film and removes organic ligand residues, yielding a high-purity dielectric layer . By carefully controlling the plasma energy and deposition chemistry, the intrinsic mechanical stress can be heavily modulated—incorporating tensile or compressive stress to induce carrier mobility enhancements in the underlying MOSFET channels through piezoresistance effects, following the strain-engineering principles essential for nanometer-scale devices [P4, T2]. Silicon nitride (SiNx) or silicon carbonitride (SiCN) is specifically selected for CESL 2 due to its excellent dielectric properties and high differential etch selectivity relative to the silicon oxide-based PMD layers that will be deposited next . Using plasma-assisted low-temperature methods over LPCVD is mandated because the high temperatures (≥700 °C) of LPCVD would exceed the thermal budget of the integrated high-k/metal gate stacks, causing interlayer diffusion and threshold voltage shifts [P2, T2]. Parameter interactions in this step are highly coupled: increasing RF plasma power enhances film density and wet-etch resistance by promoting cross-linking, but excessive ion bombardment may induce structural damage or shift the film's intrinsic stress profile unfavorably . Additionally, modulating the precursor gas flow ratios alters the stoichiometry (e.g. (Engineering Practice), the N/Si atomic ratio), which directly controls both the mechanical stress level and the material's refractive index, a crucial consideration for minimizing optical crosstalk and internal reflections in back-illuminated (BSI) image sensors . At the 40nm technology node, scaling dictates extremely tight gate pitches, necessitating atomic-scale thickness control and excellent conformality to prevent pinch-off or voiding between adjacent structures . The subthreshold leakage current is highly sensitive to gate control limits; therefore, optimized strain from the CESL 2 layer helps improve the drive current (Ion) to off-current (Ioff) ratio without indefinitely lowering the threshold voltage, effectively mitigating the thermodynamic limits of static power dissipation . Furthermore, in a BSI CIS architecture, minimizing defect-state densities across all dielectric interfaces is critical to suppressing dark current, driving the requirement for highly dense, low-hydrogen-content SiNx films achieved via advanced plasma-assisted nitridation [P1, P3].

[High] Poor Conformality and Void Formation: In highly scaled 3D topographies, radical recombination and directional ion bombardment during plasma processing can limit the flux of active species into narrow gaps between gates . This geometric shadowing leads to premature pinch-off at the top of the gap, creating voids within the CESL or subsequent PMD layer that trap contaminants and cause integration failures .
[High] Inadequate Etch Selectivity (Punch-Through): If the deposition temperature is too low or plasma densification is insufficient, the SiNx film will exhibit high impurity content and a reduced physical density . This failure to achieve a robust Si-N network severely degrades its differential etch selectivity against the PMD oxide during contact etching, leading to the etch punching through the CESL and damaging the underlying source/drain regions .
[Medium] Thermal Budget Exceedance: Exceeding the allowable deposition temperature can cause unwanted interdiffusion within the fragile high-k/metal gate stack or premature dopant diffusion out of the source/drain junctions . This thermal degradation shifts the threshold voltage and increases subthreshold leakage, violating the strict electrostatic control required for advanced MOSFETs .
[Medium] Excessive or Mismatched Mechanical Stress: While intrinsic stress is engineered for mobility enhancement, extreme tensile or compressive stress can cause the thin film to exceed its fracture toughness or delaminate from the underlying CESL 1 . Such mechanical failure modes disrupt the continuous etch-stop barrier and can induce detrimental piezoelectric dark current in the underlying silicon photodiodes .
[Low] Plasma-Induced Damage (PID): High-energy ions and ultraviolet radiation generated by the RF plasma can penetrate the thin underlying protective layers, generating interface traps and fixed oxide charges in the gate dielectric [P3, T1]. These defect states act as generation-recombination centers, directly degrading the 1/f noise performance and escalating dark current in the final image sensor (Engineering Practice).

CESL 2 deposition forms a silicon nitride or silicon carbonitride layer that prevents over-etching during contact via generation .

Following dopant activation and the initial CESL 1 deposition, the CESL 2 deposition completes the Contact Etch Stop Layer stack before the thick Pre-Metal Dielectric

[High] Poor Conformality and Void Formation: In highly scaled 3D topographies, radical recombination and directional ion bombardment during plasma processing can limit the flux of active species into narrow gaps between gates . This geometric shadowing leads to premature pinch-off at the top of the gap, creating voids within the CESL or subsequent PMD layer that trap contaminants and cause integration failures .
[High] Inadequate Etch Selectivity (Punch-Through): If the deposition temperature is too low or plasma densification is insufficient, the SiNx film will exhibit high impurity content and a reduced physical density . This failure to achieve a robust Si-N network severely degrades its differential etch selectivity against the PMD oxide during contact etching, leading to the etch punching through the CESL and damaging the underlying source/drain regions .
[Medium] Thermal Budget Exceedance: Exceeding the allowable deposition temperature can cause unwanted interdiffusion within the fragile high-k/metal gate stack or premature dopant diffusion out of the source/drain junctions . This thermal degradation shifts the threshold voltage and increases subthreshold leakage, violating the strict electrostatic control required for advanced MOSFETs .
[Medium] Excessive or Mismatched Mechanical Stress: While intrinsic stress is engineered for mobility enhancement, extreme tensile or compressive stress can cause the thin film to exceed its fracture toughness or delaminate from the underlying CESL 1 . Such mechanical failure modes disrupt the continuous etch-stop barrier and can induce detrimental piezoelectric dark current in the underlying silicon photodiodes .
[Low] Plasma-Induced Damage (PID): High-energy ions and ultraviolet radiation generated by the RF plasma can penetrate the thin underlying protective layers, generating interface traps and fixed oxide charges in the gate dielectric [P3, T1]. These defect states act as generation-recombination centers, directly degrading the 1/f noise performance and escalating dark current in the final image sensor (Engineering Practice).

40nm BSI CMOS Image SensorPreview

Process Cross-Section

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In depth

Risks & Challenges

40nm BSI CMOS Image SensorPreview

Process Cross-Section

Step highlight

In depth

Risks & Challenges