40nm BSI CMOS Image SensorPreview

ight shield grid requires extremely precise photolithography (Engineering Practice). Prior processing steps, such as the Optical Pad 3 Deposition, introduce surface topography comprising distinct peaks and valleys over the underlying optical elements [A1]. The Optical Pad 3 CMP (Chemical Mechanical Planarization) step is integrated into the flow to eliminate this topography and achieve rigorous wafer-level global planarization [P4]. Attaining a highly planar dielectric surface is an absolute prerequisite to satisfy the stringent depth of focus (DoF) limitations of the subsequent Mid Vertical Grid Trench photoresist patterning step [A1]. Without this planarization, local step heights would distort the optical field during lithography, compromising the dimensional integrity of the nanoscale-node pixel grid (Engineering Practice). The core mechanism of the CMP process operates through the continuous, synergistic interplay of chemical reactions and mechanical abrasion at the slurry–pad–wafer interface [P1]. Initially, chemical additives within the slurry react with the Optical Pad 3 dielectric, forming a nanoscale, chemically modified hydration layer whose mechanical strength is significantly reduced compared to the bulk film [P4]. Subsequently, nanoscale abrasive particles suspended in the slurry, supported by the asperities of the rotating polymer polishing pad, engage this softened surface in sliding and indentation contacts [P3]. This interaction induces microscale plastic cutting and ploughing, effectively removing the reacted layer [P3]. The macroscopic material removal rate is largely governed by Preston's law, increasing linearly with applied down-pressure and relative rotational velocity [A1]. However, this rate is fundamentally modulated at the microscale by the statistical distribution of abrasive sizes and the pad's periodic surface roughness [P3]. CMP was selected as the planarization method because purely chemical etching cannot achieve global planarity, and pure mechanical polishing generates unacceptable surface damage [P4]. The success of this step heavily relies on meticulous slurry design to balance the chemical surface-layer formation rate with the mechanical removal rate [P4]. Process parameters such as slurry pH and ionic strength are precisely tuned to regulate the electric double-layer thickness and surface charge of both the abrasives and the wafer [P4]. This electrostatic tuning is critical, as it determines the attraction or repulsion between the particles and the film, directly dictating whether residual abrasives will strongly adhere to the wafer as yield-detracting contaminants [P1]. Additionally, closed-loop temperature control systems are often utilized to preheat and stabilize the slurry temperature on the polishing pad, ensuring that the chemical reaction kinetics remain uniform and predictable across the entire wafer surface [A2]. At the 40nm technology node, the extreme sensitivity of the device layout necessitates careful management of pattern-dependent polishing effects [P2]. CMP material removal is not strictly global; it is strongly influenced by local layout features, where variations in underlying pattern density alter the actual pad-to-wafer contact state and local pressure distribution [P2]. To mitigate the risk of over-polishing high-density regions while under-polishing low-density areas, the process often employs dielectric materials with distinct mechanical hardnesses or relies on motor torque endpoint detection [A1]. This ensures the polishing naturally stops when a uniform planar surface is formed, leaving the critical underlying optical elements completely and safely buried [A1].