40nm BSI CMOS Image SensorPreview

Ashing & Strip/Clean

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Mid Vertical Grid Deposition

W CMP
346Optical Pad 3 Deposition347Optical Pad 3 CMP348Post CMP Cleaning349Pre Litho Cleaning350Mid Vertical Grid Trench - Photo351Optical Pad 3 Etch352Lower OCL Coating Etch353Lower OCL Etch354Optical Pad 2 Etch355Ashing & Strip/Clean356Mid Vertical Grid Deposition357W CMP358Post CMP Cleaning359Upper Vertical Grid Barrier Deposition360Upper Vertical Grid Deposition361Pre Litho Cleaning362Upper Vertical Grid - Photo363W Etch364TiN Etch365Ashing & Strip/Clean366Upper Grid Seal Layer Deposition367Pre Litho Cleaning

Process Cross-Section

ISP WaferCIS Wafer · BacksideLS_GRID · L32 · Mid Vertical Grid DepositionTaOAlOP+ implanted regionSiCESLSiO2CuTaAlOptical Pad 3Lower OCLSiNSiONOptical Pad 1Grid SealWTiNBPMD

Step highlight

Through efficient metal fill processes, continuous isolation barriers are formed in nanoscale trenches, ensuring strict spatial confinement of light within individual pixels .

In depth

In a 40nm BSI CMOS Image Sensor (CIS), pixel pitches are extremely small, leading to severe optical and electrical crosst

alk (Engineering Practice). To mitigate this, deep trench isolation structures filled with opaque metals, known as vertical grids or light shields, are fabricated between pixels (Engineering Practice). Following the etching and cleaning of the grid trenches, the Mid Vertical Grid Deposition step fills these high-aspect-ratio trenches with a highly reflective and optically dense material, typically tungsten (W) . This step prepares the wafer for the subsequent W CMP, which will remove the overburden to planarize the grid structure, similar to standard metal plug planarization techniques . Unlike the aperture grid located near the surface, this "mid" grid serves as the primary barrier corresponding to the deep photodiode regions, where incident photons are absorbed to generate electron-hole pairs . Through efficient metal fill processes, continuous isolation barriers are formed in nanoscale trenches, ensuring strict spatial confinement of light within individual pixels . The deposition relies on the Chemical Vapor Deposition (CVD) of tungsten, governed by the thermal chemical reduction of tungsten hexafluoride (WF6) . The process fundamentally consists of two stages: forming a thin nucleation layer via silane (SiH4) reduction, followed by bulk fill via hydrogen (H2) reduction . The nucleation phase utilizes a rapid reaction ($3SiH_4 + 2WF_6 \rightarrow 2W + 2SiF_4 + 6H$) to provide active sites on the underlying barrier . To overcome the poor step coverage typical of continuous SiH4 reduction in deep trenches, a pulsed CVD approach is employed . This introduces an atomic layer deposition (ALD)-like time-sequenced reaction that alternates WF6/SiH4 exposure with inert gas purges, preventing gas-phase reactions and ensuring uniform surface-controlled nucleation . Subsequently, the bulk fill relies on H2 reduction ($WF_6 + 3H_2 \rightarrow W + 6HF$), which is a highly conformal, temperature-driven process . Because trench dimensions in the 40nm node are smaller than the gas mean free path, reactant transport is dominated by Knudsen diffusion rather than bulk diffusion . Tungsten is selected over other metals due to its excellent optical opacity, high melting point, and a coefficient of thermal expansion that closely matches silicon . The CVD method is chosen over Physical Vapor Deposition (PVD) because PVD suffers from severe geometric shadowing in high-aspect-ratio structures, leading to premature pinch-off and void formation . During the bulk H2 reduction phase, the deposition rate is jointly determined by temperature and H2 partial pressure . Lowering the process temperature improves step coverage by reducing the surface reaction rate, allowing sufficient unreacted WF6 to diffuse to the trench bottom before being consumed . However, this inherently reduces throughput, which is actively compensated by increasing the H2 partial pressure, thereby shifting the kinetics toward a mass-transport-limited regime without sacrificing geometric conformality . At the 40nm node, the steep aspect ratios of the grid trenches dramatically exacerbate reactant depletion along the depth profile . Furthermore, the integration sequence must carefully balance the overall thermal budget to prevent degradation of the underlying photodiode junctions . Excessive thermal cycles could alter the carefully engineered bandgap properties or cause unwanted dopant diffusion, negatively impacting the crystal's periodic potential and carrier transport mechanisms . Therefore, optimizing the low-temperature H2 reduction and pulsed CVD nucleation are critical to achieving a void-free, low-stress tungsten grid that provides absolute optical isolation without compromising the intrinsic device physics.

Risks & Challenges

  • [High] Center Seam or Void Formation: In high-aspect-ratio trenches, if the surface reaction rate is too high relative to the Knudsen diffusion rate, WF6 reactants are heavily depleted near the trench opening . This leads to accelerated growth at the top and premature pinch-off, leaving a central void that can trap CMP slurry in the subsequent planarization step (Engineering Practice).
  • [Medium] High Film Stress and Delamination: Operating at elevated H2 partial pressures to maintain deposition throughput at low temperatures significantly increases the intrinsic stress of the deposited tungsten film . Excessive stress may cause the grid to delaminate from the sidewall barrier or induce mechanical damage during thermal cycling, due to slight mismatches in the coefficient of thermal expansion .
  • [Medium] Volcano Defects from WF6 Attack: If the initial SiH4-reduced nucleation layer is too thin or non-conformal, the highly reactive WF6 precursor used during the bulk fill stage can penetrate and chemically attack the underlying layers . This localized chemical attack creates structural "volcano" defects that disrupt the integrity of the grid (Engineering Practice).
  • [Low] WF6 Precursor Starvation: Pushing the process into a mass-transport-limited regime by using extremely high H2/WF6 ratios to boost low-temperature deposition rates can lead to complete WF6 consumption . This starvation causes severe intra-wafer non-uniformity, particularly between dense pixel arrays and isolated test structures, making process window control highly difficult .

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Related steps

  • LS/Aperture Grid Barrier Deposition
  • LS/Aperture Grid Deposition
  • Oxide Grid Seal Layer Deposition
  • Pre Litho Cleaning
  • Light Shield/Aperture Grid - Photo
  • Oxide Grid Seal Layer Etch